公开(公告)号：US10680764B2

公开(公告)日：2020-06-09

申请号：US15893428

申请日：2018-02-09

Applicant: QUALCOMM Incorporated

Inventor： Chi-Yuen Young ,  Jaeyoung Kwak

IPC: H04L1/18 ,  H04L1/00 ,  H03M13/00 ,  H03M13/11

Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) encoding. At least a portion of the parity bits generated by an LDPC encoder for an initial transmission may be stored for use in generating subsequent hybrid automatic repeat request (HARQ) redundancy versions. In some examples, at least the degree-two and degree-three parity bits included in the initial transmission may be stored. The parity bits may be stored within a layer 2 (L2) or an upper layer buffer or within the LDPC encoder. For example, the parity bits may be stored within the HARQ buffer.

公开(公告)号：US10447303B2

公开(公告)日：2019-10-15

申请号：US15849590

申请日：2017-12-20

Applicant: QUALCOMM Incorporated

Inventor： Chi-Yuen Young ,  Jaeyoung Kwak

IPC: H03M13/11 ,  H03M13/00 ,  H04L1/00

Abstract: Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.

公开(公告)号：US20190190543A1

公开(公告)日：2019-06-20

申请号：US15849590

申请日：2017-12-20

Applicant: QUALCOMM Incorporated

Inventor： Chi-Yuen Young ,  Jaeyoung Kwak

IPC: H03M13/00 ,  H03M13/11

CPC classification number: H03M13/616 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/6502 ,  H03M13/6516 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/0045

Abstract: Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.

公开(公告)号：US20190253199A1

公开(公告)日：2019-08-15

申请号：US15893428

申请日：2018-02-09

Applicant: QUALCOMM Incorporated

Inventor： Chi-Yuen Young ,  Jaeyoung Kwak

IPC: H04L1/18 ,  H04L1/00

CPC classification number: H04L1/1819 ,  H03M13/116 ,  H03M13/1188 ,  H03M13/616 ,  H03M13/618 ,  H03M13/6306 ,  H03M13/6502 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/1874

Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) encoding. At least a portion of the parity bits generated by an LDPC encoder for an initial transmission may be stored for use in generating subsequent hybrid automatic repeat request (HARQ) redundancy versions. In some examples, at least the degree-two and degree-three parity bits included in the initial transmission may be stored. The parity bits may be stored within a layer 2 (L2) or an upper layer buffer or within the LDPC encoder. For example, the parity bits may be stored within the HARQ buffer.