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8 条记录 (耗时 0.017 秒)

    Low-density parity check (LDPC) incremental parity-check matrix rotation
    3.
    发明授权
    Low-density parity check (LDPC) incremental parity-check matrix rotation 有权

    公开(公告)号：US10447303B2

    公开(公告)日：2019-10-15

    申请号：US15849590

    申请日：2017-12-20

    申请人： QUALCOMM Incorporated

    发明人： Chi-Yuen Young ,  Jaeyoung Kwak

    IPC分类号： H03M13/11 ,  H03M13/00 ,  H04L1/00

    摘要： Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.

    Low-density parity check (LDPC) parity bit storage for redundancy versions
    6.
    发明授权
    Low-density parity check (LDPC) parity bit storage for redundancy versions 有权

    公开(公告)号：US10680764B2

    公开(公告)日：2020-06-09

    申请号：US15893428

    申请日：2018-02-09

    申请人： QUALCOMM Incorporated

    发明人： Chi-Yuen Young ,  Jaeyoung Kwak

    IPC分类号： H04L1/18 ,  H04L1/00 ,  H03M13/00 ,  H03M13/11

    摘要： Aspects of the present disclosure relate to low density parity check (LDPC) encoding. At least a portion of the parity bits generated by an LDPC encoder for an initial transmission may be stored for use in generating subsequent hybrid automatic repeat request (HARQ) redundancy versions. In some examples, at least the degree-two and degree-three parity bits included in the initial transmission may be stored. The parity bits may be stored within a layer 2 (L2) or an upper layer buffer or within the LDPC encoder. For example, the parity bits may be stored within the HARQ buffer.

    METHOD FOR ARBITRATION AND ADAPTIVE POWER-CYCLING IN A MULTI-CHANNEL NETWORK
    8.
    发明申请
    METHOD FOR ARBITRATION AND ADAPTIVE POWER-CYCLING IN A MULTI-CHANNEL NETWORK 有权
    多通道网络中的仲裁和自适应功率循环的方法

    公开(公告)号：US20160302257A1

    公开(公告)日：2016-10-13

    申请号：US14685334

    申请日：2015-04-13

    申请人： QUALCOMM Incorporated

    发明人： Wolfgang Roethig ,  Jaeyoung Kwak

    IPC分类号： H04W76/04 ,  H04W72/04 ,  H04W72/12 ,  H04W52/02

    CPC分类号： H04W72/1263 ,  H04L5/0005 ,  H04L5/0041 ,  H04L5/0053 ,  H04W52/0216 ,  H04W52/0251 ,  H04W52/028 ,  H04W72/0453 ,  H04W76/28 ,  Y02D70/00 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/26

    摘要： A method, an apparatus, and a computer program product for data communication are provided. The method may include providing a plurality of data channels on a communications link, determining unused bandwidth as a difference between total bandwidth provided by the communications link and bandwidth used by the plurality of data channels, allocating the unused bandwidth to a virtual channel, scheduling the plurality of data channels and the virtual channel in accordance with a time-based multiplexing scheme, and disabling interface circuitry used to couple the transmitter to the communications link when the virtual channel is scheduled. Each of the plurality of data channels may be assigned to a source of data to be transmitted on the communications link.

    摘要翻译： 提供了一种用于数据通信的方法，装置和计算机程序产品。 该方法可以包括在通信链路上提供多个数据信道，将未使用的带宽确定为由通信链路提供的总带宽与多个数据信道使用的带宽之间的差异，将未使用的带宽分配给虚拟信道，调度 多个数据信道和虚拟信道，并且当虚拟信道被调度时禁用用于将发射机耦合到通信链路的接口电路。 多个数据信道中的每一个可被分配给要在通信链路上发送的数据源。