公开(公告)号：US20250094268A1

公开(公告)日：2025-03-20

申请号：US18468479

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Chintalapati BHARATH SAI VARMA

IPC: G06F11/07 ,  G06F13/42

Abstract: Various embodiments include methods and devices for efficiently recovering from errors that occur in part but not all of a universal chiplet interconnect express (UCIe) link for chiplets of a computing device. Various embodiments may include identifying a first part of a UCIe link in which an error has occurred, and training the first part of the UCIe link in which the error has occurred while maintaining active a second part of the UCIe link in which no error has occurred.

公开(公告)号：US20250103499A1

公开(公告)日：2025-03-27

申请号：US18472642

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Chintalapati BHARATH SAI VARMA ,  Prakhar SRIVASTAVA ,  Hung VUONG ,  Ravi Kumar SEPURI

IPC: G06F12/084 ,  G06F12/02

Abstract: A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).

公开(公告)号：US20240411481A1

公开(公告)日：2024-12-12

申请号：US18530074

申请日：2023-12-05

Applicant: QUALCOMM Incorporated

Inventor： Chintalapati BHARATH SAI VARMA ,  Santhosh Reddy AKAVARAM ,  Sai Naresh GAJAPAKA ,  Hung VUONG ,  Radhakrishna MUGADA ,  Prakhar SRIVASTAVA ,  Vamsi Krishna SAMBANGI

IPC: G06F3/06

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for optimizing usage of a shared write booster buffer to extend lifetime. The method may include writing data to a flash storage device including a plurality of logical units of memory by receiving a command identifying a logical unit among the plurality of logical units to store data and data for storage in the identified logical unit, obtaining information indicating a memory write type for the identified logical unit, and writing the received data to either a shared write booster buffer before writing to the identified logical unit of device storage or directly to the identified logical unit of device storage based on the obtained memory write type

公开(公告)号：US20250117144A1

公开(公告)日：2025-04-10

申请号：US18481616

申请日：2023-10-05

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Chintalapati BHARATH SAI VARMA ,  Prakhar SRIVASTAVA ,  Sai Jitendra Varma GADIRAJU

IPC: G06F3/06

Abstract: A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to be increased. The FMD includes a plurality of memory resources that include a plurality of logical units (LUs) and at least the particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric of the particular memory resource.

公开(公告)号：US20250085861A1

公开(公告)日：2025-03-13

申请号：US18464874

申请日：2023-09-11

Applicant: QUALCOMM INCORPORATED

Inventor： Santhosh Reddy AKAVARAM ,  Chintalapati BHARATH SAI VARMA ,  Prakhar SRIVASTAVA ,  Sri Ananda Sai JANNABHATLA ,  Reddy Vijay GUDI

IPC: G06F3/06 ,  G06F12/10

Abstract: Systems and methods improve write performance of a UFS device comprising N logical units (LUNs) and N write buffers (WBs), where N is a positive integer. Each WB is mapped to a respective LUN. Each WB has a respective WB lifetime estimate value and a respective WB lifetime threshold (TH) value. A determination is made as to whether the WB lifetime estimate value associated with at least a first WB of the N WBs is equal to or is greater than the respective WB TH value, and if so, the first WB is remapped to a second LUN of the N LUNs and a second WB of the N WBs is remapped to the first LUN. The remapping is based at least in part on the WB lifetime estimate value associated with the second WB indicating that the second WB has more lifetime remaining than the first WB.

公开(公告)号：US20250044982A1

公开(公告)日：2025-02-06

申请号：US18364277

申请日：2023-08-02

Applicant: QUALCOMM Incorporated

Inventor： Sai Naresh GAJAPAKA ,  Chintalapati BHARATH SAI VARMA ,  Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Vamsi Krishna SAMBANGI

IPC: G06F3/06

Abstract: Aspects relate to interrupting memory access during background operations of a memory device. In one example a memory device includes a memory controller to initiate a write buffer flush operation. A bus interface is coupled to a main memory and to a write buffer to receive a write command from a host during the write buffer flush operation. The memory controller initiates the write buffer flush operation, suspends the write buffer flush operation in response to the write command, sends a last flushed address of the write buffer from the memory device to the host through the bus interface, and unmaps a portion of the write buffer using the last flushed address.