公开(公告)号：US20240402923A1

公开(公告)日：2024-12-05

申请号：US18327691

申请日：2023-06-01

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Hung VUONG ,  Sonali JABREVA ,  Khushboo KUMARI

IPC: G06F3/06

Abstract: Aspects of the present disclosure are directed to techniques and procedures for storing data in a data storage device that uses nonvolatile memory (NVM) to store data. The NVM can be organized into logical units that are assigned respective logical unit numbers. The data storage device can report to a host the amount of spare blocks needed for one or more logical units (LUs), and then the host can relinquish some memory blocks to be reallocated as spare blocks. The data storage device can implement a spare block resource management policy per LU and allocate a predetermined amount of spare blocks per LU. The data storage device can implement a spare block resource management policy per memory type and allocate a predetermined amount of spare blocks for LUs with the same memory type.

公开(公告)号：US20250097341A1

公开(公告)日：2025-03-20

申请号：US18469370

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Gaurav SINGH ,  Sridhar ANUMALA ,  Subrato Kumar DE ,  Mugdha Sanjay PATIL ,  Ankur BHATTACHARJEE

IPC: H04M3/22 ,  H04M3/436

Abstract: Systems and techniques are provided for wireless communications. A process can include determining that a quantity of a plurality of Mobile Terminated (MT) calls received within a first time period is greater than a first configured threshold. A process can include determining a subset of non-verified MT calls from the plurality of MT calls based on a call verification score for each respective MT call of the plurality of MT calls received within the first time period. A process can include determining that a quantity of non-verified MT calls included in the subset is greater than a second configured threshold. A process can include performing modem-level blocking based on determining a corresponding calling party identity associated with a non-verified MT call included in the subset.

公开(公告)号：US20240348437A1

公开(公告)日：2024-10-17

申请号：US18301305

申请日：2023-04-17

Applicant: QUALCOMM Incorporated

Inventor： Sridhar ANUMALA ,  Bharani BHUVANAGIRI ,  Nishanth KUMAR ,  Dhananjayan ATHIYAPPAN ,  Madhu Yashwanth BOENAPALLI

IPC: H04L9/08

CPC classification number: H04L9/088 ,  H04L9/0819

Abstract: Various embodiments include methods implemented in a processor for management of cryptographic keys of an integrated cryptographic engine. Embodiments may include detecting a cryptographic key access control event, determining whether the cryptographic key access control event is for disabling cryptographic key access at a cryptographic key memory of the integrated cryptographic engine, disabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is for disabling cryptographic key access at the cryptographic key memory, and maintaining one or more cryptographic keys at the cryptographic key memory for which cryptographic key access is disabled. Embodiments may further include enabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is not for disabling cryptographic key access at the cryptographic key memory.

公开(公告)号：US20250094268A1

公开(公告)日：2025-03-20

申请号：US18468479

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Chintalapati BHARATH SAI VARMA

IPC: G06F11/07 ,  G06F13/42

Abstract: Various embodiments include methods and devices for efficiently recovering from errors that occur in part but not all of a universal chiplet interconnect express (UCIe) link for chiplets of a computing device. Various embodiments may include identifying a first part of a UCIe link in which an error has occurred, and training the first part of the UCIe link in which the error has occurred while maintaining active a second part of the UCIe link in which no error has occurred.

公开(公告)号：US20250013572A1

公开(公告)日：2025-01-09

申请号：US18347359

申请日：2023-07-05

Applicant: QUALCOMM Incorporated

Inventor： Sonali JABREVA ,  Sridhar ANUMALA ,  Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Manish GARG

IPC: G06F12/0855 ,  G06F12/02

Abstract: Aspects relate to interrupting memory access during background operations of a memory device. In one example, a host for a memory device includes background operation circuitry configured to permit a background operation by a memory device. The host is coupled to the memory device through a bus. The host receives an operation completed notification from the memory device to indicate that the memory device has completed performing the background operation. Memory access command circuitry is configured to receive a memory access command. The memory access command concerns reading or writing data to the memory device coupled to the host. The memory access command circuitry initiates a wait at the host for the memory access command, and sends the memory access command to the memory device in response to receiving the operation completed notification.

公开(公告)号：US20240427709A1

公开(公告)日：2024-12-26

申请号：US18338653

申请日：2023-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Santhosh Reddy AKAVARAM ,  Prakhar SRIVASTAVA ,  Sridhar ANUMALA ,  Ramacharan SUNDARARAMAN ,  Sonali JABREVA ,  Khushboo KUMARI ,  Sanjay VERDU

IPC: G06F13/16

Abstract: Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.