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    MULTICORE FRAMEWORK FOR USE IN PRE-BOOT ENVIRONMENT OF A SYSTEM-ON-CHIP
    3.
    发明申请
    MULTICORE FRAMEWORK FOR USE IN PRE-BOOT ENVIRONMENT OF A SYSTEM-ON-CHIP 审中-公开

    公开(公告)号：US20190095220A1

    公开(公告)日：2019-03-28

    申请号：US16137226

    申请日：2018-09-20

    Applicant: QUALCOMM Incorporated

    Inventor： Ajay IYENGAR ,  Yugandhar NARAYANA ,  Dhamim PACKER ALI ,  Sreenivasulu Reddy CHALAMCHARLA ,  Daison DAVIS KOOLA

    IPC: G06F9/4401 ,  G06F9/48 ,  G06F9/54 ,  G06F15/78

    Abstract: Various aspects are described herein. In some aspects, the disclosure provides a method of enabling a multicore framework in a pre-boot environment for a system-on-chip (SoC) comprising a plurality of processors comprising a first processor and a second processor. The method includes initiating, by the first processor, bootup of the SoC into a pre-boot environment. The method further includes scheduling, by the first processor, execution of one or more boot-up tasks by a second processor. The method further includes executing, by the second processor, the one or more boot-up tasks in the pre-boot environment. The method further includes executing, by the first processor, one or more additional tasks in parallel with the second processor executing the one or more boot-up tasks.

    SECURE SELECTIVE LOAD OF DYNAMIC PAGED SEGMENTS IN MEMORY CONSTRAINED SYSTEMS
    5.
    发明申请
    SECURE SELECTIVE LOAD OF DYNAMIC PAGED SEGMENTS IN MEMORY CONSTRAINED SYSTEMS 审中-公开

    公开(公告)号：US20190080093A1

    公开(公告)日：2019-03-14

    申请号：US15702628

    申请日：2017-09-12

    Applicant: QUALCOMM Incorporated

    Inventor： Eugen PIRVU ,  Dhamim PACKER ALI ,  Dhaval Patel ,  Bhargav GURAPPADI

    IPC: G06F21/57 ,  G06F9/44 ,  H04L9/06 ,  H04L9/32

    Abstract: Techniques for the secure loading of dynamic paged segments are provided. An example method according to the disclosure includes determining a first hash value for each of one or more pageable segments associated with a device, authenticating the one or more pageable segments based on the first hash values, determining a second hash value for each of the one or more pageable segments, transferring the second hash values for each of the pageable segments to the device, determining a load hash value for a loading pageable segment when the loading pageable segment is to be loaded into the device, comparing the load hash value with the second hash value associated with the loading pageable segment, and loading the loading pageable segment in the device when the load hash value matches the second hash value associated with the loading pageable segment.

    MULTITHREAD FRAMEWORK FOR USE IN PRE-BOOT ENVIRONMENT OF A SYSTEM-ON-CHIP
    6.
    发明申请
    MULTITHREAD FRAMEWORK FOR USE IN PRE-BOOT ENVIRONMENT OF A SYSTEM-ON-CHIP 审中-公开

    公开(公告)号：US20190332425A1

    公开(公告)日：2019-10-31

    申请号：US16203386

    申请日：2018-11-28

    Applicant: QUALCOMM Incorporated

    Inventor： Yugandhar NARAYANA ,  Dhamim PACKER ALI ,  Ajay IYENGAR ,  Kedar ATHAWALE ,  Eric TALLET

    IPC: G06F9/48 ,  G06F9/52 ,  G06F9/38

    Abstract: Various aspects are described herein. In some aspects, the disclosure provides a method for a system-on-chip (SoC) including one or more computing cores. The method includes providing a scheduler to schedule running of threads on the one or more computing cores in a pre-boot environment including a core thread configured to provide a plurality of services. The method further includes providing, by the scheduler, a first lock for the core thread. The method further includes initializing, by the core thread, one or more additional services separate from the plurality of services. The method further includes selectively allowing access to the plurality of services of the core thread to one or more additional threads based on a status of the first lock. The method further includes allowing access to the one or more additional services to the one or more additional threads independent of the status of the first lock.

    Partitioning Flash And Enabling Flexible Boot With Image Upgrade Capabilities
    7.
    发明申请
    Partitioning Flash And Enabling Flexible Boot With Image Upgrade Capabilities 审中-公开

    公开(公告)号：US20190042278A1

    公开(公告)日：2019-02-07

    申请号：US15669257

    申请日：2017-08-04

    Applicant: QUALCOMM Incorporated

    Inventor： Eugen PIRVU ,  Dhamim PACKER ALI ,  Benish BABU ,  Leonard WIDRA ,  Darshana ADVANI

    IPC: G06F9/44

    Abstract: Various aspects include methods for implementing a reduced size firmware storage format on a computing device. Various aspects may include storing a first firmware description table to a first sector of a flash memory, in which the first firmware description table may define a first instance of a firmware including describing a first plurality of firmware images, storing the first plurality of firmware images to a first plurality of consecutive sectors, storing a second firmware description table to a second sector, in which the second firmware description table may define a second instance of the firmware including describing a second plurality of firmware images having a third plurality of firmware images, storing the third plurality of firmware images to a second plurality of consecutive sectors, and booting the computing device using the second firmware description table.

    SELECTABLE BOOT CPU
    10.
    发明申请
    SELECTABLE BOOT CPU 审中-公开

    公开(公告)号：US20180253314A1

    公开(公告)日：2018-09-06

    申请号：US15448232

    申请日：2017-03-02

    Applicant: QUALCOMM Incorporated

    Inventor： Dhamim PACKER ALI ,  Yanru LI ,  Ashutosh SHRIVASTAVA ,  Azzedine TOUZNI ,  Mamta DESAI

    IPC: G06F9/44

    Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of operating a system-on-chip (SoC). The method includes selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of the quality of the plurality of CPU cores stored on the SoC. The method includes running boot code on the selected CPU.

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