公开(公告)号：US20200226964A1

公开(公告)日：2020-07-16

申请号：US16247920

申请日：2019-01-15

Applicant: QUALCOMM Incorporated

Inventor： Dileep Marchya ,  Dhaval Kanubhai Patel ,  Gopikrishnaiah Andandan

IPC: G09G3/20 ,  G06T1/60 ,  G06T1/20 ,  G06T1/00 ,  G06T11/20

Abstract: An improved method and system for power-efficient display are provided. Burst mode display processing allows a host processor to compose and render multiple low-resolution frames in a computation cycle. The low-resolution frames are transferred to a display panel, and the host processor enters a power-saving mode and minimizes power consumption while the frames are being displayed. In one embodiment, the host processor drives frame switches at the display panel while in a power-saving mode. In another embodiment, the display panel drives frame switches itself with no further input from the host processor.

公开(公告)号：US20200059643A1

公开(公告)日：2020-02-20

申请号：US16104488

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Dileep Marchya ,  Dhaval Kanubhai Patel ,  Gopikrishnaiah Andandan

IPC: H04N19/107 ,  H04N19/50 ,  H04N19/172 ,  H04N19/182 ,  H04N19/176

Abstract: Methods, systems, and devices for processing display data are described. A device may receive a bitstream sequence including a quantity of intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. In some examples, the device may be a decoding device or an encoding device. Upon receiving the bitstream sequence, the device may determine a refresh pixel region for a frame based on an order of the quantity of intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. In some examples, the order may be an encoding order of the intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. The device may then send the refresh pixel region for the frame to a display device based on determining the refresh pixel region for the frame.

公开(公告)号：US11200866B1

公开(公告)日：2021-12-14

申请号：US17176767

申请日：2021-02-16

Applicant: QUALCOMM Incorporated

Inventor： Dileep Marchya ,  Sudeep Ravi Kottilingal ,  Srinivas Pullakavi ,  Dhaval Kanubhai Patel ,  Prashant Nukala ,  Nagamalleswararao Ganji ,  Mohammed Naseer Ahmed ,  Mahesh Aia ,  Kalyan Thota ,  Sushil Chauhan

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/00

Abstract: In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.

公开(公告)号：US20210183007A1

公开(公告)日：2021-06-17

申请号：US16714019

申请日：2019-12-13

Applicant: QUALCOMM Incorporated

Inventor： Dileep Marchya ,  Dhaval Kanubhai Patel ,  Gopikrishnaiah Andandan

IPC: G06T1/60 ,  G09G5/377

Abstract: Methods, systems, and devices for image processing are described. A device may determine one or more static layers of a layer stack and one or more updating layers of the layer stack. The device may determine an order of the one or more static layers, or the one or more updating layers, or both in the layer stack. In some examples, the device may modify the order in the layer stack by positioning the one or more static layers below the one or more updating layers in the layer stack. Each static layer of the one or more static layers may be associated with a first blending equation and each updating layer of the one or more updating layers may be associated with a second blending equation. As a result, the device may process the layer stack based on the modified order.

公开(公告)号：US20250086746A1

公开(公告)日：2025-03-13

申请号：US18466498

申请日：2023-09-13

Applicant: QUALCOMM Incorporated

Inventor： Srinivas Pullakavi ,  Dileep Marchya ,  Padmanabhan Komanduru V ,  Mahesh Aia ,  Dhaval Kanubhai Patel ,  Kalyan Thota ,  Sumit Gemini

IPC: G06T1/20 ,  G06F3/147

Abstract: Optimizing compositor workload in steady state in processor devices is disclosed herein. In some aspects, a processor device is configured to perform image compositing by executing a compositor pipeline that comprises a compositor including a workload handler; a composer Hardware Abstraction Layer (HAL); a workload governor communicatively coupled to the composer HAL; and a display driver. The workload governor detects that the image compositing has entered a steady state, and transmits an indication to enter an accelerated mode to the workload handler. Upon receiving the indication, the workload handler places the compositor pipeline in the accelerated mode. While in the accelerated mode, the compositor transmits accelerated mode data directly to the display driver, bypassing the composer HAL.

公开(公告)号：US10014693B2

公开(公告)日：2018-07-03

申请号：US15162369

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Dileep Marchya ,  Dhaval Kanubhai Patel ,  Ujwal Patel ,  Nagamalleswararao Ganji ,  Mastan Manoj Kumar Amara Venkata ,  Panneer Arumugam

IPC: H02J3/14 ,  H02J4/00

CPC classification number: H02J4/00 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The disclosure relates to a system including a set of subsystems sharing a voltage rail. The system includes a power controller configured to send messages, such as interrupts, to the subsystems concerning a change of state of a supply voltage on the voltage rail. Such messages may have been sent in response to requests and messages from the subsystems, respectively. In response to the messages, the subsystems may send requests to the power controller for different dynamic clock voltage scaling (DCVS) levels, respectively. In response to such requests, the power controller may set the supply voltage and frequencies of clock signals for the requesting subsystems, respectively.

公开(公告)号：US10965944B2

公开(公告)日：2021-03-30

申请号：US16458647

申请日：2019-07-01

Applicant: QUALCOMM Incorporated

Inventor： Gopikrishnaiah Andandan ,  Dhaval Kanubhai Patel ,  Dileep Marchya ,  Nagamalleswararao Ganji

IPC: G06F13/14 ,  H04N19/164 ,  G09G5/00 ,  H04N19/174 ,  H04N19/42

Abstract: In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving, at a hardware voting component associated with a destination subsystem, metadata for each of a plurality of compressed display tiles, wherein for each of the plurality of compressed display tiles the metadata indicates an amount of compression of the compressed display tile. In some configurations, the method includes dividing the plurality of compressed display tiles into a plurality of sets of compressed display tiles. In some configurations, for each of the plurality of sets of compressed display tiles, the method includes determining a desired bandwidth for communicating the set of compressed display tiles over a bus, and receiving the set of compressed display tiles at the destination subsystem over the bus at an actual bandwidth that is based on the desired bandwidth.

公开(公告)号：US10685630B2

公开(公告)日：2020-06-16

申请号：US16004327

申请日：2018-06-08

Applicant: QUALCOMM Incorporated

Inventor： Carlos Javier Moreira ,  Paul Chow ,  Dhaval Kanubhai Patel

IPC: G09G5/36 ,  G09G5/397

Abstract: According to various aspects, just-in-time system bandwidth changes may be implemented in hardware to optimize power consumption and performance in an electronic device. More particularly, in a periodic system associated with an electronic device, a bandwidth for a next frame may be configured during a current frame via software operating on the electronic device. Hardware associated with the periodic system may issue a bandwidth change request for the next frame when a current time reaches a bandwidth increase threshold in response to actual processing time associated with the current frame finishing prior to the bandwidth increase threshold, which may be defined relative to a timer deadline that defines when the next frame starts to process.

公开(公告)号：US20170338661A1

公开(公告)日：2017-11-23

申请号：US15162369

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Dileep Marchya ,  Dhaval Kanubhai Patel ,  Ujwal Patel ,  Nagamalleswararao Ganji ,  Mastan Manoj Kumar Amara Venkata ,  Panneer Arumugam

IPC: H02J4/00

CPC classification number: H02J4/00 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: The disclosure relates to a system including a set of subsystems sharing a voltage rail. The system includes a power controller configured to send messages, such as interrupts, to the subsystems concerning a change of state of a supply voltage on the voltage rail. Such messages may have been sent in response to requests and messages from the subsystems, respectively. In response to the messages, the subsystems may send requests to the power controller for different dynamic clock voltage scaling (DCVS) levels, respectively. In response to such requests, the power controller may set the supply voltage and frequencies of clock signals for the requesting subsystems, respectively.