公开(公告)号：US20210375747A1

公开(公告)日：2021-12-02

申请号：US16889645

申请日：2020-06-01

申请人： QUALCOMM Incorporated

发明人： Ramesh MANCHANA ,  Sudheer Chowdary GALI ,  Biswa Ranjan PANDA ,  Dhaval SEJPAL ,  Stanley Seungchul SONG

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

摘要： A substrate tie cell on an IC is provided. The substrate tie cell includes a diffusion region. The diffusion region is a p-type diffusion region on or within a p-type substrate, an n-type diffusion region on or within an n-type well within a p-type substrate, an n-type diffusion region on or within an n-type substrate, or a p-type diffusion region on or within a p-type well within an n-type substrate. The substrate tie cell further includes a plurality of adjacent gate interconnects (n adjacent gate interconnects) extending over the diffusion region, where n≥4. The diffusion region is configured to be at one of a first voltage or a second voltage, and the gate interconnects are configured to be at an other of the first voltage or the second voltage. In one configuration, the first voltage is a power supply voltage and the second voltage is a ground voltage.

公开(公告)号：US20210058280A1

公开(公告)日：2021-02-25

申请号：US16984896

申请日：2020-08-04

申请人： QUALCOMM Incorporated

发明人： Chulkyu LEE ,  Dhaval SEJPAL ,  George Alan WILEY

IPC分类号： H04L27/20 ,  H04L27/227 ,  H04L27/233

摘要： Certain disclosed methods, apparatus, and systems enable improved communication on a multiphase communication link through improved encoding techniques and protocol. A data communication apparatus has a plurality of line drivers configured to couple the apparatus to a 3-wire link, and a data encoder configured to encode at least 3 bits of binary data in each transition between two symbols that are consecutively transmitted by the plurality of line drivers over the 3-wire link such that each pair of consecutively-transmitted symbols comprises two different symbols. Each symbol defines signaling states of the 3-wire link during an associated symbol transmission interval such that each wire of the 3-wire link is in a different signaling state from the other wires of the 3-wire link during the associated symbol transmission interval. Data may be encoded using a combination of 3-phase and pulse amplitude modulation.

公开(公告)号：US20190356519A1

公开(公告)日：2019-11-21

申请号：US16526332

申请日：2019-07-30

申请人： QUALCOMM Incorporated

发明人： Shih-Wei CHOU ,  Chulkyu LEE ,  Dhaval SEJPAL

IPC分类号： H04L25/493 ,  H04L25/02

摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.

公开(公告)号：US20180337698A1

公开(公告)日：2018-11-22

申请号：US16050603

申请日：2018-07-31

申请人： QUALCOMM Incorporated

发明人： Shih-Wei CHOU ,  Chulkyu LEE ,  Dhaval SEJPAL

IPC分类号： H04B1/04 ,  H04L25/493 ,  H04L25/02 ,  G06F13/40 ,  H04B3/52

CPC分类号： H04L25/493 ,  H04L25/02 ,  H04L25/0276

摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.