公开(公告)号：US20240096750A1

公开(公告)日：2024-03-21

申请号：US17933187

申请日：2022-09-19

申请人： QUALCOMM Incorporated

发明人： Qingqing LIANG ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN ,  Stanley Seungchul SONG

IPC分类号： H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L29/417

CPC分类号： H01L23/481 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/5283 ,  H01L27/1203 ,  H01L29/41725

摘要： Disclosed are integrated circuit structures with through-substrate vias (TSVs) processed through self-aligned contact modules. As a result, much smaller and/or denser TSVs are formed with low mechanical stress. The denser TSVs allow for more flexible wiring options.

公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC分类号： H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

摘要： Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20220077109A1

公开(公告)日：2022-03-10

申请号：US17015308

申请日：2020-09-09

申请人： QUALCOMM Incorporated

发明人： Bharani CHAVA ,  Stanley Seungchul SONG ,  Abinash ROY ,  Jonghae KIM

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

摘要： An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：US20210217699A1

公开(公告)日：2021-07-15

申请号：US16738127

申请日：2020-01-09

申请人： QUALCOMM Incorporated

发明人： John Jianhong ZHU ,  Stanley Seungchul SONG ,  Kern RIM

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

摘要： Certain aspects of the present disclosure generally relate to integration of a hybrid conductor material in power rails of a semiconductor device. An example semiconductor device generally includes an active electrical device and a power rail. The power rail is electrically coupled to the active electrical device, disposed above the active electrical device, and embedded in at least one dielectric layer. The power rail comprises a first conductive layer, a barrier layer, and a second conductive layer comprising copper. The barrier layer is disposed between the first conductive layer and the second conductive layer.

公开(公告)号：US20190206984A1

公开(公告)日：2019-07-04

申请号：US15860005

申请日：2018-01-02

申请人： QUALCOMM Incorporated

发明人： Junjing BAO ,  Jun CHEN ,  Yangyang SUN ,  Stanley Seungchul SONG ,  Giridhar NALLAPATI

IPC分类号： H01L49/02 ,  H01L23/522

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

摘要： Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.

公开(公告)号：US20160322391A1

公开(公告)日：2016-11-03

申请号：US15210420

申请日：2016-07-14

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L29/20 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

摘要： A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

公开(公告)号：US20150155364A1

公开(公告)日：2015-06-04

申请号：US14093105

申请日：2013-11-29

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul SONG ,  Choh Fei YEAP

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66651 ,  H01L21/28035 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

摘要： A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively.

摘要翻译： 完全耗尽的绝缘体上硅MOSFET晶体管，其阈值电压变化较小。 掺杂晶体管的衬底以在掩埋氧化物层下方形成接地层。 在掩埋氧化物层上形成轻掺杂沟道。 在沟道上形成氮氧化硅的栅极电介质，并且在栅极电介质上形成多晶硅栅极。 对于p型掺杂沟道（对于n沟道MOSFET），多晶硅栅极被掺杂以具有不大于4.2电子伏特的功函数，对于n型掺杂沟道（对于p型掺杂沟道），功率不小于5.0电子伏特， 通道MOSFET）。 掩埋氧化物层和沟道的厚度不必分别大于20纳米和10纳米。

公开(公告)号：US20150145070A1

公开(公告)日：2015-05-28

申请号：US14283168

申请日：2014-05-20

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L27/088

CPC分类号： H01L29/4238 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0886

摘要： Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length.

摘要翻译： 在模具上制造器件的方法以及管芯上的器件。 一种方法可以包括图案化第一区域以产生具有第一栅极长度的第一栅极和具有第一工艺的第一接触多晶硅间距（CPP）。 第一个CPP小于单一图案光刻极限。 该方法还包括图案化第一区域以产生具有第二栅极长度的第二栅极或具有第二工艺的第二CPP。 第二CPP小于单模光刻极限。 第二栅极长度不同于第一栅极长度。

公开(公告)号：US20240055356A1

公开(公告)日：2024-02-15

申请号：US18492402

申请日：2023-10-23

申请人： QUALCOMM Incorporated

发明人： Bharani CHAVA ,  Abinash ROY ,  Stanley Seungchul SONG ,  Jonghae KIM

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC分类号： H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227

摘要： A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; a first bridge coupled to the first integrated device and the second integrated device through at least a third plurality of solder interconnects, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device, through at least the third plurality of solder interconnects; and a second bridge coupled to the first integrated device and the second integrated device through a fourth plurality of solder interconnects.

公开(公告)号：US20230384367A1

公开(公告)日：2023-11-30

申请号：US17804658

申请日：2022-05-31

申请人： QUALCOMM Incorporated

发明人： Yangyang SUN ,  Amer Christophe Gaetan CASSIER ,  Stanley Seungchul SONG ,  Lily ZHAO ,  Dongming HE

IPC分类号： G01R31/28 ,  H01L23/00

CPC分类号： G01R31/2884 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2924/1431 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14515 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/11916 ,  H01L2224/11903 ,  H01L2224/0401 ,  H01L2224/05573 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05147 ,  H01L2224/05124 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/13147 ,  H01L2224/13005 ,  H01L2224/13016

摘要： Disclosed are integrated circuit structures with interconnects of small size, also referred to micro-bumps. As pitches of micro-bumps become smaller, their sizes also become small. This makes it difficult to probe the integrated circuit structure to verify their operations. To enable probing, test pads of larger pitches are provided. The test pads, usually formed of metal, may be protected with solder caps.