公开(公告)号：US20240321631A1

公开(公告)日：2024-09-26

申请号：US18190024

申请日：2023-03-24

申请人： QUALCOMM Incorporated

发明人： Xia LI ,  Junjing BAO ,  Bin YANG ,  Biswa Ranjan PANDA ,  Ramesh MANCHANA

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L23/5329

摘要： An integrated circuit (IC) includes back-end-of-line (BEOL) interconnects in a first intermetal dielectric (IMD) layer on a substrate. The IC also includes second BEOL interconnects on the first IMD layer, coupled to the first BEOL interconnects through first BEOL vias in the first IMD layer. The IC further includes a second IMD layer on the second BEOL interconnects to seal airgaps between the plurality of second BEOL interconnects. The IC also includes etch stop spacers on portions of sidewalls of the second BEOL interconnects to separate the portions of the sidewalls from the second IMD layer. The IC further includes third BEOL interconnects on the second IMD layer and coupled to one or more of the second BEOL interconnects through second BEOL vias in the second IMD layer.

公开(公告)号：US20210375747A1

公开(公告)日：2021-12-02

申请号：US16889645

申请日：2020-06-01

申请人： QUALCOMM Incorporated

发明人： Ramesh MANCHANA ,  Sudheer Chowdary GALI ,  Biswa Ranjan PANDA ,  Dhaval SEJPAL ,  Stanley Seungchul SONG

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

摘要： A substrate tie cell on an IC is provided. The substrate tie cell includes a diffusion region. The diffusion region is a p-type diffusion region on or within a p-type substrate, an n-type diffusion region on or within an n-type well within a p-type substrate, an n-type diffusion region on or within an n-type substrate, or a p-type diffusion region on or within a p-type well within an n-type substrate. The substrate tie cell further includes a plurality of adjacent gate interconnects (n adjacent gate interconnects) extending over the diffusion region, where n≥4. The diffusion region is configured to be at one of a first voltage or a second voltage, and the gate interconnects are configured to be at an other of the first voltage or the second voltage. In one configuration, the first voltage is a power supply voltage and the second voltage is a ground voltage.