公开(公告)号：US20230087277A1

公开(公告)日：2023-03-23

申请号：US17481601

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hochul LEE ,  Anil Chowdary KOTA ,  Dhvani SHETH ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

公开(公告)号：US20230395139A1

公开(公告)日：2023-12-07

申请号：US17833852

申请日：2022-06-06

Applicant: QUALCOMM Incorporated

Inventor： Dhvani SHETH ,  Hochul LEE ,  Anil Chowdary KOTA ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

公开(公告)号：US20250022494A1

公开(公告)日：2025-01-16

申请号：US18349918

申请日：2023-07-10

Applicant: QUALCOMM Incorporated

Inventor： Hochul LEE ,  Anil Chowdary KOTA ,  Dhvani SHETH ,  Bin LIANG ,  Chulmin JUNG

IPC: G11C7/10 ,  G11C7/08

Abstract: A memory is provided with a pair of banks including a first bank of bitcells and a second bank of bitcells. An I/O circuit for the pair of banks includes a shared write path configured to couple a write driver input signal to the first bank of bitcells responsive to an assertion of a write enable signal for the first bank of bitcells and to couple the write driver input signal to the second bank of bitcells responsive to an assertion of a write enable signal for the second bank of bitcells. The I/O circuit also includes a shared read path configured to couple a data bit output signal from the first bank of bitcells to a sense amplifier responsive to a de-assertion of the write enable signal for the first bank of bitcells and to couple a data bit output signal from the second bank of bitcells to the sense amplifier responsive to a de-assertion of the write enable signal for the second bank of bitcells. The shared read and write paths are further configured to operate simultaneously so that a write operation to one of the banks may occur while a read operation occurs to another one of the banks.

公开(公告)号：US20240395320A1

公开(公告)日：2024-11-28

申请号：US18796143

申请日：2024-08-06

Applicant: QUALCOMM Incorporated

Inventor： Dhvani SHETH ,  Hochul LEE ,  Anil Chowdary KOTA ,  Chulmin JUNG

IPC: G11C11/419 ,  G11C11/418

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

公开(公告)号：US20230317150A1

公开(公告)日：2023-10-05

申请号：US17657231

申请日：2022-03-30

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Xiao CHEN ,  Chi-Jui CHEN ,  Anil Chowdary KOTA ,  Dhvani SHETH

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.