公开(公告)号：US20210350865A1

公开(公告)日：2021-11-11

申请号：US16868402

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Bin LIANG ,  Chi-Jui CHEN

IPC: G11C29/02 ,  G11C29/20 ,  G11C29/10 ,  G11C29/12 ,  G11C29/44 ,  G11C29/00

Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.

公开(公告)号：US20250022494A1

公开(公告)日：2025-01-16

申请号：US18349918

申请日：2023-07-10

Applicant: QUALCOMM Incorporated

Inventor： Hochul LEE ,  Anil Chowdary KOTA ,  Dhvani SHETH ,  Bin LIANG ,  Chulmin JUNG

IPC: G11C7/10 ,  G11C7/08

Abstract: A memory is provided with a pair of banks including a first bank of bitcells and a second bank of bitcells. An I/O circuit for the pair of banks includes a shared write path configured to couple a write driver input signal to the first bank of bitcells responsive to an assertion of a write enable signal for the first bank of bitcells and to couple the write driver input signal to the second bank of bitcells responsive to an assertion of a write enable signal for the second bank of bitcells. The I/O circuit also includes a shared read path configured to couple a data bit output signal from the first bank of bitcells to a sense amplifier responsive to a de-assertion of the write enable signal for the first bank of bitcells and to couple a data bit output signal from the second bank of bitcells to the sense amplifier responsive to a de-assertion of the write enable signal for the second bank of bitcells. The shared read and write paths are further configured to operate simultaneously so that a write operation to one of the banks may occur while a read operation occurs to another one of the banks.

公开(公告)号：US20180068714A1

公开(公告)日：2018-03-08

申请号：US15258964

申请日：2016-09-07

Applicant: QUALCOMM Incorporated

Inventor： Bin LIANG ,  Tony Chung Yiu KWOK ,  Rui LI ,  Sei Seung YOON

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C7/1072 ,  G11C7/227 ,  G11C8/18 ,  G11C11/419 ,  G11C13/0061

Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.