公开(公告)号：US20210350865A1

公开(公告)日：2021-11-11

申请号：US16868402

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Bin LIANG ,  Chi-Jui CHEN

IPC: G11C29/02 ,  G11C29/20 ,  G11C29/10 ,  G11C29/12 ,  G11C29/44 ,  G11C29/00

Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.

公开(公告)号：US20230317150A1

公开(公告)日：2023-10-05

申请号：US17657231

申请日：2022-03-30

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Xiao CHEN ,  Chi-Jui CHEN ,  Anil Chowdary KOTA ,  Dhvani SHETH

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

公开(公告)号：US20250095698A1

公开(公告)日：2025-03-20

申请号：US18469989

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Sonia GHOSH ,  Xiao CHEN ,  Chi-Jui CHEN

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

Abstract: A random-access memory has its bitcells arranged into a first pair of banks and a second pair of banks. The first pair of banks and second pair of banks are separated by a central controller that contains sense amplifiers and write drivers for the first pair of banks and for the second pair of banks.

公开(公告)号：US20240428831A1

公开(公告)日：2024-12-26

申请号：US18340807

申请日：2023-06-23

Applicant: QUALCOMM Incorporated

Inventor： Chi-Jui CHEN ,  Xiao CHEN ,  Sonia GHOSH ,  Hochul LEE ,  Anil Chowdary KOTA ,  Giby SAMSON

IPC: G11C5/14 ,  G11C11/417

Abstract: A circuit is provided with a selectively diode-connected head switch transistor. During a light-sleep mode, the head switch transistor is diode connected so that a power supply voltage passing through the diode-connected head switch transistor is reduced by a transistor threshold voltage drop. During an active mode, the diode connection is opened so that the head switch transistor passes a power supply voltage with virtually no voltage drop.