公开(公告)号：US09466536B2

公开(公告)日：2016-10-11

申请号：US14451342

申请日：2014-08-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Stuart B. Molin ,  George P. Imthurn

IPC: H01L21/30 ,  H01L21/00 ,  H01L21/46 ,  H01L21/84 ,  H01L21/762 ,  H01L21/3213 ,  H01L23/48 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76256 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for manufacturing semiconductor-on-insulator (SOI) integrated circuits are disclosed. An SOI wafer is provided having a first surface and a second surface. The substrate of the SOI wafer forms the second surface. A transistor is formed in the semiconductor layer of the SOI wafer. A handle wafer is bonded to the first surface of the SOI wafer. The substrate layer is then removed to expose a back surface of the buried insulator of the SOI wafer. Conductive material is deposited on the SOI wafer that covers the back surface of the buried insulator. The conductive material is patterned to form a second gate electrode for the transistor on the back surface of the insulator.

Abstract translation: 公开了制造绝缘体上半导体（SOI）集成电路的方法。 提供具有第一表面和第二表面的SOI晶片。 SOI晶片的衬底形成第二表面。 晶体管形成在SOI晶片的半导体层中。 把手晶片结合到SOI晶片的第一表面。 然后去除衬底层以暴露SOI晶片的埋入绝缘体的背表面。 导电材料沉积在覆盖掩埋绝缘体背面的SOI晶片上。 将导电材料图案化以形成用于绝缘体背面上的晶体管的第二栅电极。