公开(公告)号：US20190304898A1

公开(公告)日：2019-10-03

申请号：US15936907

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Plamen Vassilev KOLEV ,  Michael Andrew STUBER ,  Lee-Wen CHEN

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/78 ,  H01L23/66 ,  H01L29/423 ,  H01L21/762 ,  H01L21/28

Abstract: A transistor may include a semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The channel region may have a source interface and a drain interface, and may be bounded by edges extending from the source interface to the drain interface on two boundaries between a field-sensitive semiconductor material and an isolation material. The transistor may further include an insulator layer on the channel region. The transistor may further include a gate on the insulator layer. The gate may have extensions beyond edges of the channel region. The extensions may substantially exceed a minimum specified value.

公开(公告)号：US20180076137A1

公开(公告)日：2018-03-15

申请号：US15807169

申请日：2017-11-08

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Plamen Vassilev KOLEV ,  Michael Andrew STUBER ,  Richard HAMMOND ,  Shiqun GU ,  Steve FANELLI

IPC: H01L23/528 ,  H04B1/16 ,  H01L49/02 ,  H01L23/532 ,  H01L23/522 ,  H01L29/06 ,  H01L27/12 ,  H01L23/66

CPC classification number: H01L23/5283 ,  H01L23/5223 ,  H01L23/53209 ,  H01L23/66 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/94 ,  H01L2223/6677 ,  H04B1/16

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.