公开(公告)号：US20180301419A1

公开(公告)日：2018-10-18

申请号：US15658296

申请日：2017-07-24

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/02 ,  H01L21/304 ,  H01L21/306

Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.

公开(公告)号：US20190131454A1

公开(公告)日：2019-05-02

申请号：US15800916

申请日：2017-11-01

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238

Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. A strain inducing intermediate layer (SIIL) is on the porous silicon layer. A silicon layer is on the SIIL. Lattice constant of the silicon layer is different from lattice constant of the SIIL. Thus, the silicon layer is strained. By employing different strain inducing materials in the SIIL, the silicon layer can be used to form different complementary metal oxide semiconductor (CMOS) transistors with improved characteristics.

公开(公告)号：US20180277632A1

公开(公告)日：2018-09-27

申请号：US15669704

申请日：2017-08-04

Applicant: QUALCOMM Incorporated

Inventor： Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/10 ,  H01L21/683 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02 ,  H01L21/20 ,  H01L21/306 ,  H01L23/528 ,  H01L23/00 ,  H01L29/78

Abstract: An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

公开(公告)号：US20180233604A1

公开(公告)日：2018-08-16

申请号：US15431623

申请日：2017-02-13

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Gengming TAO ,  Richard HAMMOND ,  Ranadeep DUTTA ,  Matthew Michael NOWAK ,  Francesco CAROBOLANTE

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/22 ,  H01L29/47 ,  H01L29/737 ,  H01L29/66 ,  H01L27/06 ,  H01L21/822 ,  H01L23/00 ,  H01L23/66 ,  H03H11/34 ,  H03H11/04

CPC classification number: H01L29/93 ,  H01L21/8221 ,  H01L23/66 ,  H01L24/13 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/20 ,  H01L29/22 ,  H01L29/47 ,  H01L29/66174 ,  H01L29/66242 ,  H01L29/7371 ,  H01L2224/13025 ,  H03H11/04 ,  H03H11/342

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

公开(公告)号：US20210098600A1

公开(公告)日：2021-04-01

申请号：US16589444

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep DUTTA ,  Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/737

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region, a collector region, and a base region disposed between the emitter region and the collector region, the base region and the collector region comprising different semiconductor materials. The HBT device may also include an etch stop layer disposed between the collector region and the base region. The HBT device also includes an emitter contact, wherein the emitter region is between the emitter contact and the base region, and a collector contact, wherein the collector region is between the collector contact and the base region.

公开(公告)号：US20190181218A1

公开(公告)日：2019-06-13

申请号：US15836122

申请日：2017-12-08

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Stephen Alan FANELLI ,  Richard HAMMOND

IPC: H01L29/04 ,  H01L29/10 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a porous silicon layer on a silicon substrate. The semiconductor device also includes a seal layer on the porous silicon layer. The semiconductor device further includes a high charge carrier mobility material layer on the seal layer. The semiconductor device may further include a strain balancing intermediate layer between the seal layer and the high charge carrier mobility material layer. Different high charge carrier mobility materials can be used in the high charge carrier mobility material layer to form different semiconductor devices.

公开(公告)号：US20180076137A1

公开(公告)日：2018-03-15

申请号：US15807169

申请日：2017-11-08

Applicant: QUALCOMM Incorporated

Inventor： Sinan GOKTEPELI ,  Plamen Vassilev KOLEV ,  Michael Andrew STUBER ,  Richard HAMMOND ,  Shiqun GU ,  Steve FANELLI

IPC: H01L23/528 ,  H04B1/16 ,  H01L49/02 ,  H01L23/532 ,  H01L23/522 ,  H01L29/06 ,  H01L27/12 ,  H01L23/66

CPC classification number: H01L23/5283 ,  H01L23/5223 ,  H01L23/53209 ,  H01L23/66 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/94 ,  H01L2223/6677 ,  H04B1/16

Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.

公开(公告)号：US20180068886A1

公开(公告)日：2018-03-08

申请号：US15256341

申请日：2016-09-02

Applicant: QUALCOMM Incorporated

Inventor： Richard HAMMOND ,  Sinan GOKTEPELI

IPC: H01L21/762 ,  H01L21/84 ,  H01L23/66 ,  H01L27/12 ,  H01Q1/22

CPC classification number: H01L21/76259 ,  H01L21/76256 ,  H01L21/7806 ,  H01L21/84 ,  H01L23/66 ,  H01L27/1203 ,  H01L2223/6677 ,  H01Q1/2283

Abstract: An integrated radio frequency (RF) circuit structure may include an active device on a front-side surface of a semiconductor device layer. A backside surface opposite the front-side surface of the semiconductor device layer may be supported by a backside dielectric layer. The integrated RF circuit structure may also include a handle substrate on a front-side dielectric layer that is on a front-side of the active device and a least a portion of the front-side surface of the semiconductor device layer. The integrated RF circuit structure may further include the backside dielectric layer on the backside surface of the semiconductor device layer. The backside dielectric layer may be arranged distal from the front-side dielectric layer.