公开(公告)号：US20240256827A1

公开(公告)日：2024-08-01

申请号：US18565414

申请日：2021-07-27

Applicant: QUALCOMM Incorporated

Inventor： Sameer WADHWA ,  Suren MOHAN ,  Peiyu ZHU ,  Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes computation circuitry configured to perform a convolution operation, the computation circuitry having multiple input rows, and an activation buffer having multiple buffer segments coupled to the multiple the multiple input rows of the computation circuitry, respectively. In some aspects, each of the multiple buffer segments comprises a first multiplexer having a plurality of multiplexer inputs, and each of the plurality of multiplexer inputs of one of the first multiplexers on one of the multiple buffer segments is coupled to a data output of the activation buffer on another one of the multiple buffer segments.