公开(公告)号：US20230086802A1

公开(公告)日：2023-03-23

申请号：US17478609

申请日：2021-09-17

Applicant: QUALCOMM Incorporated

Inventor： Sameer WADHWA ,  Suren MOHAN ,  Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ ,  Jian SHEN

IPC: G06F7/50 ,  G06F3/06 ,  G06F7/523

Abstract: Certain aspects of the present disclosure provide techniques for efficient depthwise convolution. A convolution is performed with a compute-in-memory (CIM) array to generate CIM output, and at least a portion of the CIM output corresponding to a first output data channel, of a plurality of output data channels in the CIM output, is written to a digital multiply-accumulate (DMAC) activation buffer. A patch of the CIM output is read from the DMAC activation buffer, and weight data is read from a DMAC weight buffer. Multiply-accumulate (MAC) operations are performed with the patch of CIM output and the weight data to generate a DMAC output.

公开(公告)号：US20210240442A1

公开(公告)日：2021-08-05

申请号：US16779491

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ ,  Guoqing MIAO ,  Seyfi BAZARJANI

IPC: G06F7/544 ,  G11C11/419 ,  G11C11/412

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

公开(公告)号：US20220012580A1

公开(公告)日：2022-01-13

申请号：US16922953

申请日：2020-07-07

Applicant: QUALCOMM Incorporated

Inventor： Ankit SRIVASTAVA

IPC: G06N3/063 ,  H03M1/46 ,  G11C11/419 ,  G11C11/412 ,  G06N3/04 ,  G06N3/08 ,  G06F7/544

Abstract: A multiply-and-accumulate (MAC) circuit having a plurality of compute-in-memory bitcells is configured to multiply a plurality of stored weight bits with a plurality of input bits to provide a MAC output voltage. A successive approximation analog-to-digital converter includes a capacitive-digital-to-analog-converter (CDAC) configured to subtract a bias voltage from the MAC output voltage to provide a CDAC output voltage. A comparator compares the CDAC output voltage to a fixed reference voltage.

公开(公告)号：US20220301605A1

公开(公告)日：2022-09-22

申请号：US17204649

申请日：2021-03-17

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Ankit SRIVASTAVA ,  Sameer WADHWA ,  Ren LI ,  Suren MOHAN

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/10

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

公开(公告)号：US20210397937A1

公开(公告)日：2021-12-23

申请号：US17353564

申请日：2021-06-21

Applicant: QUALCOMM Incorporated

Inventor： Mustafa KESKIN ,  Ankit SRIVASTAVA ,  Sameer WADHWA ,  Guoqing MIAO

IPC: G06N3/063 ,  G11C11/54 ,  G11C5/14 ,  G06N3/08

Abstract: A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.

公开(公告)号：US20210279039A1

公开(公告)日：2021-09-09

申请号：US16811480

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Ankit SRIVASTAVA

IPC: G06F7/57 ,  G11C11/412 ,  G11C11/419

Abstract: A compute-in-memory array is provided that includes a set of compute-in-memory bitcells that time share a shared capacitor connected between the set of compute-in-memory bitcells and a read bit line.

公开(公告)号：US20210192324A1

公开(公告)日：2021-06-24

申请号：US16721819

申请日：2019-12-19

Applicant: QUALCOMM Incorporated

Inventor： Ankit SRIVASTAVA

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06F7/544 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: A near memory system is provided for the calculation of a layer in a machine learning application. The near memory system includes an array of memory cells for storing an array of filter weights. A multiply-and-accumulate circuit couples to columns of the array to form the calculation of the layer.

公开(公告)号：US20220230679A1

公开(公告)日：2022-07-21

申请号：US17152564

申请日：2021-01-19

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Xiaonan CHEN ,  Ankit SRIVASTAVA ,  Sameer WADHWA ,  Zhongze WANG

IPC: G11C11/419 ,  G06F7/544

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

公开(公告)号：US20250124354A1

公开(公告)日：2025-04-17

申请号：US18989865

申请日：2024-12-20

Applicant: QUALCOMM Incorporated

Inventor： Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ ,  Sameer WADHWA

IPC: G06N20/00 ,  H03K19/20 ,  H03M7/30

Abstract: Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.

公开(公告)号：US20240256827A1

公开(公告)日：2024-08-01

申请号：US18565414

申请日：2021-07-27

Applicant: QUALCOMM Incorporated

Inventor： Sameer WADHWA ,  Suren MOHAN ,  Peiyu ZHU ,  Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes computation circuitry configured to perform a convolution operation, the computation circuitry having multiple input rows, and an activation buffer having multiple buffer segments coupled to the multiple the multiple input rows of the computation circuitry, respectively. In some aspects, each of the multiple buffer segments comprises a first multiplexer having a plurality of multiplexer inputs, and each of the plurality of multiplexer inputs of one of the first multiplexers on one of the multiple buffer segments is coupled to a data output of the activation buffer on another one of the multiple buffer segments.