公开(公告)号：US20220301605A1

公开(公告)日：2022-09-22

申请号：US17204649

申请日：2021-03-17

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Ankit SRIVASTAVA ,  Sameer WADHWA ,  Ren LI ,  Suren MOHAN

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/10

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

公开(公告)号：US20220230679A1

公开(公告)日：2022-07-21

申请号：US17152564

申请日：2021-01-19

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Xiaonan CHEN ,  Ankit SRIVASTAVA ,  Sameer WADHWA ,  Zhongze WANG

IPC: G11C11/419 ,  G06F7/544

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

公开(公告)号：US20250096810A1

公开(公告)日：2025-03-20

申请号：US18470309

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Igor GUTMAN ,  Elias DAGHER ,  Hua WANG ,  Behnam SEDIGHI ,  Seyed Arash MIRHAJ ,  Tao LUO

IPC: H03M1/06 ,  G06N3/08 ,  H03M1/12

Abstract: A training signal generator for forming an input signal for an ADC-under-test includes a one-bit DAC and an analog low-pass filter. The one-bit DAC converts a binary sequence into a DAC output signal that is then filtered by the analog low-pass filter to form an ADC input signal. The ADC-under-test converts the ADC input signal into an ADC output signal. A digital low-pass filter converts the binary sequence into a plurality of samples. A digital signal processing system processes the plurality of samples and the ADC output signal to form an estimate of the ADC input signal. An ADC linearizer may then be trained to characterize a non-linear impairment of the ADC-under-test responsive to a comparison of the estimate of the ADC input signal and the ADC output signal.

公开(公告)号：US20230086802A1

公开(公告)日：2023-03-23

申请号：US17478609

申请日：2021-09-17

Applicant: QUALCOMM Incorporated

Inventor： Sameer WADHWA ,  Suren MOHAN ,  Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ ,  Jian SHEN

IPC: G06F7/50 ,  G06F3/06 ,  G06F7/523

Abstract: Certain aspects of the present disclosure provide techniques for efficient depthwise convolution. A convolution is performed with a compute-in-memory (CIM) array to generate CIM output, and at least a portion of the CIM output corresponding to a first output data channel, of a plurality of output data channels in the CIM output, is written to a digital multiply-accumulate (DMAC) activation buffer. A patch of the CIM output is read from the DMAC activation buffer, and weight data is read from a DMAC weight buffer. Multiply-accumulate (MAC) operations are performed with the patch of CIM output and the weight data to generate a DMAC output.

公开(公告)号：US20210240442A1

公开(公告)日：2021-08-05

申请号：US16779491

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ ,  Guoqing MIAO ,  Seyfi BAZARJANI

IPC: G06F7/544 ,  G11C11/419 ,  G11C11/412

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

公开(公告)号：US20250124354A1

公开(公告)日：2025-04-17

申请号：US18989865

申请日：2024-12-20

Applicant: QUALCOMM Incorporated

Inventor： Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ ,  Sameer WADHWA

IPC: G06N20/00 ,  H03K19/20 ,  H03M7/30

Abstract: Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.

公开(公告)号：US20240256827A1

公开(公告)日：2024-08-01

申请号：US18565414

申请日：2021-07-27

Applicant: QUALCOMM Incorporated

Inventor： Sameer WADHWA ,  Suren MOHAN ,  Peiyu ZHU ,  Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes computation circuitry configured to perform a convolution operation, the computation circuitry having multiple input rows, and an activation buffer having multiple buffer segments coupled to the multiple the multiple input rows of the computation circuitry, respectively. In some aspects, each of the multiple buffer segments comprises a first multiplexer having a plurality of multiplexer inputs, and each of the plurality of multiplexer inputs of one of the first multiplexers on one of the multiple buffer segments is coupled to a data output of the activation buffer on another one of the multiple buffer segments.

公开(公告)号：US20220291900A1

公开(公告)日：2022-09-15

申请号：US17197359

申请日：2021-03-10

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Ankit SRIVASTAVA ,  Sameer WADHWA

IPC: G06F7/544

Abstract: Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.

公开(公告)号：US20190296755A1

公开(公告)日：2019-09-26

申请号：US15936015

申请日：2018-03-26

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Masoud ENSAFDARAN ,  Lei SUN ,  Dinesh ALLADI

IPC: H03M1/08 ,  H03M1/00

Abstract: Certain aspects of the present disclosure provide methods and apparatus for performing background noise estimation using a circular histogram noise figure (CHNF) in an analog-to-digital converter (ADC) circuit with redundancy. The estimated noise may be used to reduce the noise (e.g., comparator noise) in the ADC circuit. One example ADC circuit generally includes at least one of a comparator or a digital-to-analog converter (DAC) and at least one digital feedback input. The at least one digital feedback input is coupled to the at least one of the comparator or the DAC and is configured to adjust at least one parameter of the at least one of the comparator or the DAC based on at least a portion of an output of the ADC circuit.