公开(公告)号：US20230086802A1

公开(公告)日：2023-03-23

申请号：US17478609

申请日：2021-09-17

Applicant: QUALCOMM Incorporated

Inventor： Sameer WADHWA ,  Suren MOHAN ,  Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ ,  Jian SHEN

IPC: G06F7/50 ,  G06F3/06 ,  G06F7/523

Abstract: Certain aspects of the present disclosure provide techniques for efficient depthwise convolution. A convolution is performed with a compute-in-memory (CIM) array to generate CIM output, and at least a portion of the CIM output corresponding to a first output data channel, of a plurality of output data channels in the CIM output, is written to a digital multiply-accumulate (DMAC) activation buffer. A patch of the CIM output is read from the DMAC activation buffer, and weight data is read from a DMAC weight buffer. Multiply-accumulate (MAC) operations are performed with the patch of CIM output and the weight data to generate a DMAC output.

公开(公告)号：US20230078203A1

公开(公告)日：2023-03-16

申请号：US17467079

申请日：2021-09-03

Applicant: QUALCOMM Incorporated

Inventor： Ren LI ,  Prajakt KULKARNI ,  Suren MOHAN ,  Aaron Douglass LAMB

IPC: G06N3/04 ,  G06N3/063 ,  G06F1/03

Abstract: Certain aspects of the present disclosure provide a method for processing input data by a configurable nonlinear activation function circuit, including determining a nonlinear activation function for application to input data; determining, based on the determined nonlinear activation function, a set of parameters for a configurable nonlinear activation function circuit; and processing input data with the configurable nonlinear activation function circuit based on the set of parameters to generate output data.

公开(公告)号：US20220301605A1

公开(公告)日：2022-09-22

申请号：US17204649

申请日：2021-03-17

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Ankit SRIVASTAVA ,  Sameer WADHWA ,  Ren LI ,  Suren MOHAN

IPC: G11C7/12 ,  G11C7/18 ,  G11C7/10

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

公开(公告)号：US20240256827A1

公开(公告)日：2024-08-01

申请号：US18565414

申请日：2021-07-27

Applicant: QUALCOMM Incorporated

Inventor： Sameer WADHWA ,  Suren MOHAN ,  Peiyu ZHU ,  Ren LI ,  Ankit SRIVASTAVA ,  Seyed Arash MIRHAJ

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes computation circuitry configured to perform a convolution operation, the computation circuitry having multiple input rows, and an activation buffer having multiple buffer segments coupled to the multiple the multiple input rows of the computation circuitry, respectively. In some aspects, each of the multiple buffer segments comprises a first multiplexer having a plurality of multiplexer inputs, and each of the plurality of multiplexer inputs of one of the first multiplexers on one of the multiple buffer segments is coupled to a data output of the activation buffer on another one of the multiple buffer segments.

公开(公告)号：US20230185533A1

公开(公告)日：2023-06-15

申请号：US18165802

申请日：2023-02-07

Applicant: QUALCOMM Incorporated

Inventor： Ren LI ,  Prajakt KULKARNI ,  Suren MOHAN ,  Aaron Douglass LAMB

IPC: G06F7/556 ,  G06F7/50

CPC classification number: G06F7/556 ,  G06F7/50

Abstract: Certain aspects of the present disclosure provide a method for processing input data by a set of configurable nonlinear activation function circuits, including generating an exponent output by processing input data using one or more first configurable nonlinear activation function circuits configured to perform an exponential function, summing the exponent output of the one or more first configurable nonlinear activation function circuits, and generating an approximated log softmax output by processing the summed exponent output using a second configurable nonlinear activation function circuit configured to perform a natural logarithm function.