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公开(公告)号:US11424672B2
公开(公告)日:2022-08-23
申请号:US17159082
申请日:2021-01-26
Applicant: QUALCOMM Incorporated
Inventor: Pradeep Silva , Subbarao Surendra Chakkirala , Sherif Galal
Abstract: Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limit circuit comprising a first capacitive element, a charge circuit coupled to the first capacitive element, a first current source, a first resistive element coupled to the first current source, the capacitive element being coupled to a node between the resistive element and the first current source, a sample-and-hold circuit coupled to the first capacitive element, and a clamp circuit coupled between the sample-and-hold circuit and the feedback path.
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公开(公告)号:US11424720B2
公开(公告)日:2022-08-23
申请号:US16827280
申请日:2020-03-23
Applicant: QUALCOMM Incorporated
Inventor: Pradeep Silva , Ramkumar Sivakumar , Qubo Zhou , Xinwang Zhang , Hanil Lee , Dongyang Tang , Vijayakumar Dhanasekaran
Abstract: A power amplifier provides reduction of click and pop in audio applications. The power amplifier includes a first amplifier and an auxiliary amplifier. The auxiliary amplifier is used to ramp the power amplifier output from ground to an offset voltage to reduce the “click and pop” sound. The first amplifier and the auxiliary amplifier having a shared feedback loop. An output of the first amplifier and an output of the auxiliary amplifier may be switchably coupled to the shared feedback loop. A wave generator controls a switch to couple the first amplifier output or the auxiliary amplifier output to the shared feedback loop.
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公开(公告)号:US11683015B2
公开(公告)日:2023-06-20
申请号:US17404862
申请日:2021-08-17
Applicant: QUALCOMM Incorporated
Inventor: ChienChung Yang , Dongyang Tang , Sherif Galal , Xinwang Zhang , Subbarao Surendra Chakkirala , Pradeep Silva
CPC classification number: H03F1/3205 , H03F3/2173 , H03F2200/03 , H03F2200/165 , H03F2200/351
Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.
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