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    SENSOR ARRAY WITH RECEIVER BIAS ELECTRODE
    3.
    发明申请
    SENSOR ARRAY WITH RECEIVER BIAS ELECTRODE 有权
    传感器阵列与接收器偏置电极

    公开(公告)号：US20150016223A1

    公开(公告)日：2015-01-15

    申请号：US14332242

    申请日：2014-07-15

    Applicant: QUALCOMM Incorporated

    Inventor： Timothy Dickinson ,  Lennart Karl-Axel Mathe ,  Scott McCarthy ,  Kostadin Dimitrov Djordjev ,  Louis Dominic Oliveira ,  Qubo Zhou

    IPC: G01S15/02

    CPC classification number: G06F3/043 ,  G01H1/04 ,  G01S15/02 ,  G06F3/0416 ,  G06F3/0436

    Abstract: A method of operation of an ultrasonic sensor array includes receiving a receiver bias voltage at a receiver bias electrode of the ultrasonic sensor array to bias piezoelectric sensor elements of the ultrasonic sensor array. The method further includes receiving a transmitter control signal at the ultrasonic sensor array to cause an ultrasonic transmitter of the ultrasonic sensor array to generate an ultrasonic wave. The method further includes generating data samples based on a reflection of the ultrasonic wave. The receiver bias voltage and the transmitter control signal are received from an integrated circuit that is coupled to the ultrasonic sensor array.

    Abstract translation: 超声波传感器阵列的操作方法包括在超声波传感器阵列的接收器偏置电极处接收接收器偏置电压，以偏压超声波传感器阵列的压电传感器元件。 该方法还包括在超声波传感器阵列处接收发射器控制信号以使超声波传感器阵列的超声波发射器产生超声波。 该方法还包括基于超声波的反射生成数据样本。 接收器偏置电压和发射机控制信号从耦合到超声波传感器阵列的集成电路接收。

    METHOD AND INTEGRATED CIRCUIT FOR OPERATING A SENSOR ARRAY
    4.
    发明申请
    METHOD AND INTEGRATED CIRCUIT FOR OPERATING A SENSOR ARRAY 审中-公开
    用于操作传感器阵列的方法和集成电路

    公开(公告)号：US20150015515A1

    公开(公告)日：2015-01-15

    申请号：US14332267

    申请日：2014-07-15

    Applicant: QUALCOMM Incorporated

    Inventor： Timothy Dickinson ,  Lennart Karl-Axel Mathe ,  Scott McCarthy ,  Kostadin Dimitrov Djordjev ,  Louis Dominic Oliveira ,  Qubo Zhou

    IPC: G06F3/043 ,  G01H1/04

    CPC classification number: G06F3/043 ,  G01H1/04 ,  G01S15/02 ,  G06F3/0416 ,  G06F3/0436

    Abstract: An apparatus includes an integrated circuit configured to be operatively coupled to a sensor array that is configured to generate an ultrasonic wave. The integrated circuit includes a transmitter circuit configured to provide a first signal to the sensor array. The integrated circuit further includes a receiver circuit configured to receive a second signal from the sensor array in response to providing the first signal. The sensor array includes an ultrasonic transmitter configured to generate the ultrasonic wave in response to the first signal and a piezoelectric receiver layer configured to detect a reflection of the ultrasonic wave.

    Abstract translation: 一种装置包括被配置为可操作地耦合到被配置为产生超声波的传感器阵列的集成电路。 集成电路包括被配置为向传感器阵列提供第一信号的发射器电路。 集成电路还包括接收器电路，其被配置为响应于提供第一信号而从传感器阵列接收第二信号。 传感器阵列包括响应于第一信号产生超声波的超声波发射器和被配置为检测超声波的反射的压电接收层。

    Pre-drive level shifter with compact bias generator
    6.
    发明授权
    Pre-drive level shifter with compact bias generator 有权

    公开(公告)号：US11133792B1

    公开(公告)日：2021-09-28

    申请号：US16885137

    申请日：2020-05-27

    Applicant: QUALCOMM Incorporated

    Inventor： Qubo Zhou ,  Sherif Galal

    IPC: H03K3/356 ,  H03F3/24

    Abstract: A level shifter includes a compact bias generator. The compact bias generator generates a first bias signal and a second bias signal, in the absence of a buffer. The level shifter also includes a first latch in a first stage to translate a first voltage to a second voltage based on the first bias signal. The level shifter further includes a second latch in a second stage to translate the first voltage to a third voltage based on the second bias signal. The first bias signal is independent of the second bias signal.

    Area-efficient non-overlapping signal generator
    7.
    发明授权
    Area-efficient non-overlapping signal generator 有权

    公开(公告)号：US10886904B1

    公开(公告)日：2021-01-05

    申请号：US16752412

    申请日：2020-01-24

    Applicant: QUALCOMM Incorporated

    Inventor： Qubo Zhou ,  Yan Wang

    IPC: H03K5/134 ,  H03K19/003 ,  H03K19/0185

    Abstract: Certain aspects of the present disclosure generally relate to a power stage. The power stage generally includes a first transistor, a second transistor having a drain coupled to a drain of the first transistor, a first gate drive circuit coupled between an input node of the power stage and a gate of the first transistor, and a second gate drive circuit having a first signal path coupled between the input node and a gate of the second transistor. In certain aspects, the second gate drive circuit comprises a plurality of buffers in the first signal path, and a plurality of electronic devices coupled to the plurality of buffers and configured to apply a delay associated with driving the gate of the second transistor to track a delay associated with driving the gate of the first transistor via the first gate drive circuit.

    Low power operational transconductance amplifier
    8.
    发明授权
    Low power operational transconductance amplifier 有权
    低功耗运算跨导放大器

    公开(公告)号：US09369099B1

    公开(公告)日：2016-06-14

    申请号：US14566539

    申请日：2014-12-10

    Applicant: QUALCOMM Incorporated

    Inventor： Qubo Zhou

    IPC: H03F3/45 ,  H03M3/00

    CPC classification number: H03F3/45179 ,  H03F1/086 ,  H03F3/45188 ,  H03F2200/45 ,  H03F2203/45024 ,  H03F2203/45034 ,  H03F2203/45058 ,  H03F2203/45194 ,  H03F2203/45296 ,  H03F2203/45631 ,  H03M3/458

    Abstract: A method and an apparatus relating to an amplifier (e.g., an operational transconductance amplifier or OTA) are provided. The OTA includes a first node and a second node. The OTA further includes a differential transistor pair for receiving an input. The differential transistor pair is coupled to the first node and the second node. The OTA includes a pair of output nodes for outputting a response to the input. The response at the pair of output nodes includes a first frequency pole. A capacitive element is coupled between the first node and the second node. The response includes a second frequency pole based on the capacitive element. The second frequency pole is at a greater frequency than the first frequency pole.

    Abstract translation: 提供了与放大器（例如，运算跨导放大器或OTA）相关的方法和装置。 OTA包括第一节点和第二节点。 OTA还包括用于接收输入的差分晶体管对。 差分晶体管对耦合到第一节点和第二节点。 OTA包括用于输出对输入的响应的一对输出节点。 输出节点对的响应包括第一个频率极点。 电容元件耦合在第一节点和第二节点之间。 响应包括基于电容元件的第二频率极点。 第二个频率极点处于比第一个频率极点更大的频率。

    Power efficient noise-coupled delta-sigma modulator
    9.
    发明授权
    Power efficient noise-coupled delta-sigma modulator 有权
    功率有效的噪声耦合Δ-Σ调制器

    公开(公告)号：US09184765B1

    公开(公告)日：2015-11-10

    申请号：US14485641

    申请日：2014-09-12

    Applicant: QUALCOMM Incorporated

    Inventor： Yan Wang ,  Qubo Zhou

    IPC: H03M3/00 ,  H03M1/12 ,  H04N19/126 ,  H03M1/00

    CPC classification number: H03M3/45 ,  H03M3/424

    Abstract: A method and apparatus for a feed-forward delta-sigma modulator are provided. The apparatus includes a first adder configured to receive a feedback signal and an input signal and a first integrator configured to receive an output from the first adder. The apparatus also includes a noise-coupled summer/integrator (NCSI). The NCSI includes a second adder configured to receive a differentiation path from the first integrator, an output from the first integrator, and a delayed feedback path from the output of a second integrator. The NCSI also includes the second integrator configured to receive an output from the second adder. The apparatus also includes a quantizer configured to receive the output of the second integrator, feed back the output to the first adder and the NCSI and produce the output from the feed-forward delta-sigma modulator.

    Abstract translation: 提供了一种用于前馈delta-sigma调制器的方法和装置。 该装置包括：第一加法器，被配置为接收反馈信号和输入信号;以及第一积分器，被配置为接收来自第一加法器的输出。 该装置还包括噪声耦合的加法器/积分器（NCSI）。 NCSI包括第二加法器，其被配置为从第一积分器接收微分路径，来自第一积分器的输出和来自第二积分器的输出的延迟反馈路径。 NCSI还包括被配置为从第二加法器接收输出的第二积分器。 该装置还包括被配置为接收第二积分器的输出的量化器，将输出反馈到第一加法器和NCSI并产生来自前馈delta-sigma调制器的输出。

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