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11 条记录 (耗时 0.014 秒)

    Dynamic common-mode adjustment for power amplifiers
    2.
    发明授权
    Dynamic common-mode adjustment for power amplifiers 有权

    公开(公告)号：US12028030B2

    公开(公告)日：2024-07-02

    申请号：US17648958

    申请日：2022-01-26

    申请人： QUALCOMM Incorporated

    发明人： Dongyang Tang ,  Xinwang Zhang ,  ChienChung Yang ,  Earl Schreyer ,  Sherif Galal

    IPC分类号： H03F3/217 ,  H03F3/45

    CPC分类号： H03F3/217 ,  H03F2200/03

    摘要： Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.

    Class-D amplifier with deadtime distortion compensation
    3.
    发明授权
    Class-D amplifier with deadtime distortion compensation 有权

    公开(公告)号：US11683015B2

    公开(公告)日：2023-06-20

    申请号：US17404862

    申请日：2021-08-17

    申请人： QUALCOMM Incorporated

    发明人： ChienChung Yang ,  Dongyang Tang ,  Sherif Galal ,  Xinwang Zhang ,  Subbarao Surendra Chakkirala ,  Pradeep Silva

    IPC分类号： H03F1/32 ,  H03F3/217

    CPC分类号： H03F1/3205 ,  H03F3/2173 ,  H03F2200/03 ,  H03F2200/165 ,  H03F2200/351

    摘要： A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

    Reducing Resistor Conductivity Modulation During Amplification
    5.
    发明申请
    Reducing Resistor Conductivity Modulation During Amplification 有权

    公开(公告)号：US20220263471A1

    公开(公告)日：2022-08-18

    申请号：US17597989

    申请日：2019-08-22

    申请人： Khaled Mahmoud ABDELFATTAH ALY ,  Chaoli ZHONG ,  Dongyang TANG ,  Qualcomm Incorporated

    发明人： Khaled Mahmoud Abdelfattah Aly ,  Chaoli Zhong ,  Dongyang Tang

    IPC分类号： H03F1/02 ,  H03F3/45 ,  H04R3/00

    摘要： An apparatus is disclosed for reducing resistor conductivity modulation during amplification. In an example aspect, the apparatus includes a power amplifier circuit comprising a first pair of resistors, a digital-to-analog converter comprising a second pair of resistors, a reference generation circuit comprising a third pair of resistors, and a scaling circuit. The scaling circuit is configured to accept a common-mode reference voltage and a common-mode output voltage. The scaling circuit is also configured to provide a first voltage at body terminals of the first pair of resistors, a second voltage at body terminals of the second pair of resistors, and a third voltage at body terminals of the third pair of resistors such that a summation of the first voltage and the third voltage reduced by the second voltage is approximately equal to an average of the common-mode reference voltage and the common-mode output voltage.

    Digital-to-analog converter with glitch-irrelevant reference voltage to increase linearity
    6.
    发明授权
    Digital-to-analog converter with glitch-irrelevant reference voltage to increase linearity 有权

    公开(公告)号：US10673449B1

    公开(公告)日：2020-06-02

    申请号：US16398962

    申请日：2019-04-30

    申请人： QUALCOMM Incorporated

    发明人： Chien-Chung Yang ,  Dongyang Tang ,  Vijayakumar Dhanasekaran

    IPC分类号： H03M1/06

    摘要： A digital-to-analog converter has both a plurality of DAC stages and a plurality of dummy stages. Each DAC stage causes a glitch or disturbance to a pair of reference voltages when the DAC stage changes its switching state. Each dummy stage also causes a similar glitch or disturbance to the pair of reference voltages when the dummy stage changes its switching state. The dummy stages are controlled to change their switching state responsive to how many DAC stages change their switching state such that a total glitch induced onto the reference voltages remains substantially constant across a succession of digital words converted by the digital-to-analog converter into an analog output signal.

    Reducing resistor conductivity modulation during amplification
    8.
    发明授权
    Reducing resistor conductivity modulation during amplification 有权

    公开(公告)号：US12057812B2

    公开(公告)日：2024-08-06

    申请号：US17597989

    申请日：2019-08-22

    申请人： Qualcomm Incorporated

    发明人： Khaled Mahmoud Abdelfattah Aly ,  Chaoli Zhong ,  Dongyang Tang

    IPC分类号： H03F1/02 ,  H03F3/45 ,  H04R3/00

    CPC分类号： H03F1/0211 ,  H03F3/45475 ,  H04R3/00 ,  H03F2200/03 ,  H04R2420/07

    摘要： An apparatus is disclosed for reducing resistor conductivity modulation during amplification. In an example aspect, the apparatus includes a power amplifier circuit comprising a first pair of resistors, a digital-to-analog converter comprising a second pair of resistors, a reference generation circuit comprising a third pair of resistors, and a scaling circuit. The scaling circuit is configured to accept a common-mode reference voltage and a common-mode output voltage. The scaling circuit is also configured to provide a first voltage at body terminals of the first pair of resistors, a second voltage at body terminals of the second pair of resistors, and a third voltage at body terminals of the third pair of resistors such that a summation of the first voltage and the third voltage reduced by the second voltage is approximately equal to an average of the common-mode reference voltage and the common-mode output voltage.