公开(公告)号：US20180006650A1

公开(公告)日：2018-01-04

申请号：US15367706

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03K19/0185 ,  H03K19/00 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/356113 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/0013

Abstract: In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

公开(公告)号：US09948303B2

公开(公告)日：2018-04-17

申请号：US15367751

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03L5/00 ,  H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/0013 ,  H03K19/01855 ,  H03K19/0963

Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

公开(公告)号：US09859893B1

公开(公告)日：2018-01-02

申请号：US15367706

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03K3/35 ,  H03K19/00 ,  G09G3/20 ,  H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/356113 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/0013

Abstract: In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

公开(公告)号：US20180006651A1

公开(公告)日：2018-01-04

申请号：US15367751

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/0013 ,  H03K19/01855 ,  H03K19/0963

Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.