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    Latch array with mask-write functionality
    3.
    发明授权
    Latch array with mask-write functionality 有权

    公开(公告)号：US11810636B2

    公开(公告)日：2023-11-07

    申请号：US17574431

    申请日：2022-01-12

    Applicant: QUALCOMM Incorporated

    Inventor： Rui Li ,  De Lu ,  Venkat Narayanan

    IPC: G11C7/10

    CPC classification number: G11C7/1009 ,  G11C7/1087

    Abstract: An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.

    True single phase clock (TSPC) based latch array
    4.
    发明授权
    True single phase clock (TSPC) based latch array 有权

    公开(公告)号：US11695393B2

    公开(公告)日：2023-07-04

    申请号：US17162647

    申请日：2021-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Rui Li ,  De Lu ,  Venkat Narayanan

    IPC: H03K3/037 ,  H03K19/20 ,  H04B1/40

    CPC classification number: H03K3/037 ,  H03K19/20 ,  H04B1/40

    Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

    Apparatus for design for testability of multiport register arrays
    6.
    发明授权
    Apparatus for design for testability of multiport register arrays 有权

    公开(公告)号：US09941866B2

    公开(公告)日：2018-04-10

    申请号：US15207800

    申请日：2016-07-12

    Applicant: QUALCOMM Incorporated

    Inventor： Rakesh Vattikonda ,  Samrat Sinharoy ,  De Lu

    IPC: H03K3/289 ,  H03K3/037 ,  G01R31/317 ,  G01R31/3185

    CPC classification number: H03K3/0372 ,  G01R31/31704 ,  G01R31/31723 ,  G01R31/318541

    Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

    Back end of line (BEOL) process corner sensing
    8.
    发明授权
    Back end of line (BEOL) process corner sensing 有权

    公开(公告)号：US11823962B2

    公开(公告)日：2023-11-21

    申请号：US17180652

    申请日：2021-02-19

    Applicant: QUALCOMM Incorporated

    Inventor： Saravanan Marimuthu ,  De Lu ,  Baldeo Sharan Sharma ,  Peeyush Kumar Parkar ,  Venkat Narayanan ,  Rui Li ,  Samy Shafik Tawfik Zaynoun ,  Min Chen ,  David Kidd ,  Amit Patil

    IPC: H01L21/66 ,  G06F30/398

    CPC classification number: H01L22/14 ,  G06F30/398 ,  H01L22/34

    Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

    True random number generator based on period jitter
    9.
    发明授权
    True random number generator based on period jitter 有权

    公开(公告)号：US11334321B2

    公开(公告)日：2022-05-17

    申请号：US16913631

    申请日：2020-06-26

    Applicant: QUALCOMM Incorporated

    Inventor： Rui Li ,  De Lu ,  Venkat Narayanan ,  Srivatsan Chellappa

    IPC: G06F7/58

    Abstract: A true random number generator (TRNG) for generating a sequence of random numbers of bits is disclosed. The TRNG includes a TRNG cell configured to generate a sequence of bits logically alternating with a mean frequency and with substantially random period jitter; a period monitor configured to generate a first sequence of random bits based on a set of periods of the sequence of logically alternating bits; and a sampling circuit configured to sample the first sequence of random bits in response to a sampling clock to generate a second sequence of random bits.

    Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors
    10.
    发明授权
    Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors 有权

    公开(公告)号：US10164768B1

    公开(公告)日：2018-12-25

    申请号：US15904222

    申请日：2018-02-23

    Applicant: QUALCOMM Incorporated

    Inventor： Ravindraraj Ramaraju ,  Rakesh Vattikonda ,  Samrat Sinharoy ,  De Lu ,  Bo Pang

    IPC: H04L9/00 ,  H03K19/00

    Abstract: In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

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