公开(公告)号：US09053773B2

公开(公告)日：2015-06-09

申请号：US14025741

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Saravanan Marimuthu ,  Sachin Bapat ,  Sakthivel Packirisamy

IPC: G11C7/10 ,  G11C7/00 ,  G11C7/08 ,  G11C8/16 ,  G11C8/00 ,  G11C8/12 ,  G11C8/18 ,  G11C29/00 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C8/16 ,  G11C5/06 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/18 ,  G11C29/818 ,  G11C2207/108 ,  Y10T29/49117

Abstract: An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line.

Abstract translation: 公开了一种具有存储器件的集成电路元件; P型半导体区域，包括耦合到存储器件的第一存储器端口电路的第一半导体器件，并且被配置为当第一半导体器件被激活时能够访问存储器件; N型半导体区域，包括耦合到所述存储器件的第二存储器端口电路的第二半导体器件，并且被配置为当所述第二半导体器件被激活时能够访问所述存储器件; 以及分布在P型和N型半导体区域上的多条信号线，包括耦合以允许第一半导体器件被激活的第一存储器端口选择线; 耦合以允许第二半导体器件被激活的第二存储器端口选择线; 以及设置在第一存储器端口选择线和第二存储器端口选择线之间的时钟信号线。