公开(公告)号：US20190286587A1

公开(公告)日：2019-09-19

申请号：US16262267

申请日：2019-01-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Helena Deirdre O'SHEA ,  Wolfgang ROETHIG ,  Christopher Kong Yee CHUN ,  ZhenQi CHEN ,  Scott DAVENPORT ,  Chiew-Guan TAN ,  Wilson CHEN ,  Umesh SRIKANTIAH

IPC: G06F13/24 ,  G06F13/42

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

公开(公告)号：US20190302830A1

公开(公告)日：2019-10-03

申请号：US15942191

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： ZhenQi CHEN ,  Jianguo YAO ,  Scott DAVENPORT ,  Helena Deirdre O'SHEA ,  Reza MOHAMMADPOURRAD

IPC: G06F1/04

Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

公开(公告)号：US20210081348A1

公开(公告)日：2021-03-18

申请号：US17003724

申请日：2020-08-26

Applicant: QUALCOMM Incorporated

Inventor： Reza RODD ,  Scott DAVENPORT ,  Umesh SRIKANTIAH ,  ZhenQi CHEN

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

公开(公告)号：US20210081340A1

公开(公告)日：2021-03-18

申请号：US17003697

申请日：2020-08-26

Applicant: QUALCOMM Incorporated

Inventor： Reza RODD ,  Scott DAVENPORT ,  Umesh SRIKANTIAH ,  ZhenQi CHEN

IPC: G06F13/20 ,  H04L29/08 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.