中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.015 seconds)

    TECHNIQUE FOR RFFE AND SPMI REGISTER-0 WRITE DATAGRAM FUNCTIONAL EXTENSION
    2.
    发明申请
    TECHNIQUE FOR RFFE AND SPMI REGISTER-0 WRITE DATAGRAM FUNCTIONAL EXTENSION 审中-公开

    公开(公告)号：US20190163649A1

    公开(公告)日：2019-05-30

    申请号：US16155554

    申请日：2018-10-09

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Helena Deirdre O'SHEA ,  Richard Dominic WIETFELDT ,  ZhenQi CHEN

    IPC: G06F13/16 ,  G06F3/06

    Abstract: Systems, methods, and apparatus for functionally extending a capability of a write datagram for RFFE and SPMI devices are provided. A sending device sets a configuration register to indicate an operation mode of a write command and generates a command code field in the write command. A most significant bit of the command code field has a value of 1 and remaining bits of the command code field are defined based on the operation mode. The sending device further includes payload bytes in a payload field of the write command based on the operation mode and sends the write command to a receiver via a bus interface. The sending device may also set a page-address register to include a page-address to be used if page segmented access (PSA) is enabled for the write command and set the configuration register to indicate whether the PSA for the write command is enabled.

    INTRA-MODULE SERIAL COMMUNICATION INTERFACE FOR RADIO FREQUENCY DEVICES
    4.
    发明申请
    INTRA-MODULE SERIAL COMMUNICATION INTERFACE FOR RADIO FREQUENCY DEVICES 有权

    公开(公告)号：US20210081348A1

    公开(公告)日：2021-03-18

    申请号：US17003724

    申请日：2020-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Reza RODD ,  Scott DAVENPORT ,  Umesh SRIKANTIAH ,  ZhenQi CHEN

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

    CONTROLLING THE APPLICATION TIME OF RADIO FREQUENCY FRONT END TRIGGERS BASED ON EXECUTION OF SEQUENCES
    5.
    发明申请
    CONTROLLING THE APPLICATION TIME OF RADIO FREQUENCY FRONT END TRIGGERS BASED ON EXECUTION OF SEQUENCES 有权

    公开(公告)号：US20210081340A1

    公开(公告)日：2021-03-18

    申请号：US17003697

    申请日：2020-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Reza RODD ,  Scott DAVENPORT ,  Umesh SRIKANTIAH ,  ZhenQi CHEN

    IPC: G06F13/20 ,  H04L29/08 ,  G06F13/42

    Abstract: Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.

    ON-CHIP CLOCK GENERATOR CALIBRATION
    8.
    发明申请
    ON-CHIP CLOCK GENERATOR CALIBRATION 审中-公开

    公开(公告)号：US20190302830A1

    公开(公告)日：2019-10-03

    申请号：US15942191

    申请日：2018-03-30

    Applicant: QUALCOMM Incorporated

    Inventor： ZhenQi CHEN ,  Jianguo YAO ,  Scott DAVENPORT ,  Helena Deirdre O'SHEA ,  Reza MOHAMMADPOURRAD

    IPC: G06F1/04

    Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

Patent Agency Ranking