公开(公告)号：US20200020624A1

公开(公告)日：2020-01-16

申请号：US16030936

申请日：2018-07-10

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Joan Rey Villarba BUOT ,  Soumyadipta BASU ,  Charles David PAYNTER

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A chip package substrate and methods for fabricating the chip package substrate. An exemplary chip package substrate generally includes a first substrate and a second substrate embedded in the first substrate and having a plurality of layered traces embedded therein.

公开(公告)号：US20200176417A1

公开(公告)日：2020-06-04

申请号：US16209723

申请日：2018-12-04

Applicant: QUALCOMM Incorporated

Inventor： Brigham NAVAJA ,  Yue LI ,  Kuiwon KANG ,  Soumyadipta BASU ,  Joan Rey Villarba BUOT

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H05K1/18

Abstract: The present disclosure generally relates to an integrated circuit having a stacked embedded passive substrate (EPS) structure formed therein. In particular, a substrate may have a cavity formed therein and the stacked EPS structure may include multiple passive components formed in the cavity to provide separate electrical paths for decoupling of the integrated circuit. Furthermore, the multiple passive components may each have two respective terminals such that the multiple passive components may support different voltage domains. Among other things, compared to conventional die-side and/or land-side passive components, the stacked EPS structure may advantageously reduce a z-axis height of the integrated circuit, reduce manufacturing costs, improve performance due to shorter electrical paths, and improve design routing through x-axis and y-axis space savings.