公开(公告)号：US20250096111A1

公开(公告)日：2025-03-20

申请号：US18467163

申请日：2023-09-14

Applicant: QUALCOMM Incorporated

Inventor： Michelle Yejin KIM ,  Hong Bok WE ,  Joan Rey Villarba BUOT ,  Kuiwon KANG

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A package comprising an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises a core layer comprising a cavity; a region comprising a passive component block located at least partially in the cavity of the core layer, wherein the passive component block comprises a first passive device and a second passive device; at least one dielectric layer coupled to the core layer; and a plurality of interconnects located at least partially in the at least one dielectric layer.

公开(公告)号：US20240373562A1

公开(公告)日：2024-11-07

申请号：US18310408

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Seongryul CHOI ,  Kuiwon KANG ,  Jung Won PARK

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40

Abstract: In an aspect, an electronic device is disclosed that includes a core having an upper planar surface and an interior planar surface; a cavity extending at least partially through the upper planar surface of the core to the interior planar surface of the core; an electronic component mounted in the cavity, the electronic component including an upper planar surface having one or more electronic component terminals, wherein the electronic component is supported by the interior planar surface of the core so that the upper planar surface of the electronic component is level with the upper planar surface of the core; and an upper metallization structure configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

公开(公告)号：US20210313266A1

公开(公告)日：2021-10-07

申请号：US16840752

申请日：2020-04-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate.

公开(公告)号：US20200219803A1

公开(公告)日：2020-07-09

申请号：US16724247

申请日：2019-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Chin-Kwan KIM ,  Aniket PATIL ,  Jaehyun YEON

IPC: H01L23/498 ,  H01L21/48

Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

公开(公告)号：US20200013706A1

公开(公告)日：2020-01-09

申请号：US16189128

申请日：2018-11-13

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Houssam JOMAA

IPC: H01L23/498 ,  H01L21/48

Abstract: A substrate that includes a first substrate portion, a second substrate portion and a second dielectric layer. The first substrate portion includes a core layer having a first core surface, and a plurality of core substrate interconnects, wherein the plurality of core substrate interconnects includes a plurality of surface core substrate interconnects formed over the first surface of core layer. The second substrate portion includes a first dielectric layer having a first dielectric surface, the first dielectric surface facing the first core surface of the core layer, and a plurality of substrate interconnects, wherein the plurality of substrate interconnects includes a plurality of interconnects formed over the first dielectric surface. The second dielectric layer is formed between the first substrate portion and the second substrate portion such that the plurality of surface core substrate interconnects and the plurality of substrate interconnects are located in the second dielectric layer.

公开(公告)号：US20250070034A1

公开(公告)日：2025-02-27

申请号：US18455368

申请日：2023-08-24

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Hong Bok WE ,  Michelle Yejin KIM

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device includes a substrate including first conductors connecting contacts on a first side of the substrate to contacts on a second side of the substrate. The first conductors include metal lines arranged in metal layers separated from one another by dielectric layers and conductive vias interconnecting the metal lines. The substrate also includes second conductors connecting contacts on the first side of the substrate to contacts on the first side of the substrate to define conductive paths between a first die and a second die. The second conductors include metal lines arranged in metal layers that are separated from one another by dielectric layers and conductive vias interconnecting the metal lines of the second conductors. At least one metal layer of the second conductors is devoid of the metal lines of the first conductors.

公开(公告)号：US20230282585A1

公开(公告)日：2023-09-07

申请号：US17684327

申请日：2022-03-01

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Hong Bok WE ,  Michelle Yejin KIM

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer, and a plurality of interconnects comprising a plurality of escape interconnects. The plurality of escape interconnects includes a first embedded escape interconnect, a second embedded escape interconnect, and a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect.

公开(公告)号：US20220172963A1

公开(公告)日：2022-06-02

申请号：US17107512

申请日：2020-11-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Joan Rey Villarba BUOT ,  Terence CHEUNG

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

公开(公告)号：US20210391247A1

公开(公告)日：2021-12-16

申请号：US16900672

申请日：2020-06-12

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG

IPC: H01L23/528 ,  H01L21/768

Abstract: A substrate that includes a core layer comprising a first surface and a second surface, a plurality of core interconnects located in the core layer, a high-density interconnect portion located in the core layer, a first dielectric layer coupled to the first surface of the core layer, a first plurality of interconnects located in the first dielectric layer, a second dielectric layer coupled to the second surface of the core layer, and a second plurality of interconnects located in the second dielectric layer. The high-density interconnect portion includes a first redistribution dielectric layer and a first plurality of high-density interconnects located in the first redistribution dielectric layer. The high-density interconnect portion may provide high-density interconnects.

公开(公告)号：US20210287976A1

公开(公告)日：2021-09-16

申请号：US16819732

申请日：2020-03-16

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Kuiwon KANG ,  Joonsuk PARK ,  Karthikeyan DHANDAPANI

IPC: H01L23/498 ,  H01L21/48

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate having at least two different dielectric layers with different dielectric materials and methods for fabricating the same. One example embedded trace substrate generally includes a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; and a second metal layer disposed below the second dielectric layer.