公开(公告)号：US20210104467A1

公开(公告)日：2021-04-08

申请号：US16590718

申请日：2019-10-02

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Brigham NAVAJA ,  Hong Bok WE ,  Yuzhe ZHANG

IPC: H01L23/538 ,  H01L23/495 ,  H01L23/31

Abstract: A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

公开(公告)号：US20240304503A1

公开(公告)日：2024-09-12

申请号：US18179223

申请日：2023-03-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Brigham NAVAJA

IPC: H01L21/66 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L22/32 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/0268 ,  H05K1/113 ,  H05K3/4038 ,  H05K2201/0969

Abstract: Disclosed are apparatuses and techniques for fabricating the apparatuses. In an aspect, an apparatus includes an outer connection layer. The outer connection layer has an outer substrate and an outer metallization layer (ML). The outer ML includes a first set of sense split pads. The first set of sense split pads includes a first pad portion and a second pad portion and a test line. The test line is coupled to the first pad portion. The first pad portion and the second pad portion are electrically coupled to a same interconnect.

公开(公告)号：US20200051907A1

公开(公告)日：2020-02-13

申请号：US16230896

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Marcus HSU ,  Brigham NAVAJA ,  Houssam JOMAA

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

公开(公告)号：US20210407919A1

公开(公告)日：2021-12-30

申请号：US16915199

申请日：2020-06-29

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Brigham NAVAJA

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: Conventional package problems may be overcome with a hybrid metallization and laminate structure that avoids warpage problems and size reduction problems. One example structure may include a metallization structure directly attached to an active side of a logic die stack in a core substrate (on one or both sides of the substrate) with laminate layers built-up on top of the metallization structures for a symmetrical package structure.

公开(公告)号：US20200176417A1

公开(公告)日：2020-06-04

申请号：US16209723

申请日：2018-12-04

Applicant: QUALCOMM Incorporated

Inventor： Brigham NAVAJA ,  Yue LI ,  Kuiwon KANG ,  Soumyadipta BASU ,  Joan Rey Villarba BUOT

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H05K1/18

Abstract: The present disclosure generally relates to an integrated circuit having a stacked embedded passive substrate (EPS) structure formed therein. In particular, a substrate may have a cavity formed therein and the stacked EPS structure may include multiple passive components formed in the cavity to provide separate electrical paths for decoupling of the integrated circuit. Furthermore, the multiple passive components may each have two respective terminals such that the multiple passive components may support different voltage domains. Among other things, compared to conventional die-side and/or land-side passive components, the stacked EPS structure may advantageously reduce a z-axis height of the integrated circuit, reduce manufacturing costs, improve performance due to shorter electrical paths, and improve design routing through x-axis and y-axis space savings.

公开(公告)号：US20240321709A1

公开(公告)日：2024-09-26

申请号：US18460471

申请日：2023-09-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Brigham NAVAJA ,  Hong Bok WE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/08235 ,  H01L2224/16235 ,  H01L2924/182

Abstract: A package comprising an integrated device and a metallization portion. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects comprise a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect includes a first thickness. The second metallization interconnect includes a second thickness that is different from the first thickness. The package may include a substrate and/or a bridge. The substrate may include an interposer.

公开(公告)号：US20240063195A1

公开(公告)日：2024-02-22

申请号：US17889163

申请日：2022-08-16

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Brigham NAVAJA ,  Hong Bok WE

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/162 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/182

Abstract: A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

公开(公告)号：US20210407918A1

公开(公告)日：2021-12-30

申请号：US16913288

申请日：2020-06-26

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Brigham NAVAJA ,  Marcus HSU ,  Terence CHEUNG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/522 ,  H01L49/02 ,  H01L21/48 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

公开(公告)号：US20210296280A1

公开(公告)日：2021-09-23

申请号：US16824811

申请日：2020-03-20

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Brigham NAVAJA

IPC: H01L23/00

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for connecting packages for integrated circuits or packaged assemblies with other packages or modules using flex cables. An example packaged assembly for integrated circuits includes: a first integrated circuit (IC) package, a second IC package disposed above the first IC package, and a flex cable, wherein an end of the flex cable is connected to at least one of the first IC package or the second IC package.