公开(公告)号：US10401941B2

公开(公告)日：2019-09-03

申请号：US15425980

申请日：2017-02-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ramprasath Vilangudipitchai ,  Srijith Nair ,  Mohammad Tamjidi

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/10 ,  H03K5/13

Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.

公开(公告)号：US20180224921A1

公开(公告)日：2018-08-09

申请号：US15425980

申请日：2017-02-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ramaprasath Vilangudipitchai ,  Srijith Nair ,  Mohammad Tamjidi

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/10 ,  G06F1/3296 ,  H03K5/13 ,  Y02D10/171

Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.