公开(公告)号：US09973187B1

公开(公告)日：2018-05-15

申请号：US15381322

申请日：2016-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： Harshat Pant ,  Aditya Vummannagari ,  Yeshwant Kolla

IPC: H03L7/00 ,  H03K17/22 ,  H03K3/037

CPC classification number: H03K17/223 ,  G06F1/24

Abstract: A power on reset circuit including an inverter powered by a first power domain, the inverter including a data input coupled to a power rail of a second power domain; logic circuitry coupled with an output of the inverter, the logic circuitry having a control signal output; and wherein, during a power up operation, the first power domain powers up before the second power domain powers up. Upon power up of the first power domain, the inverter can output a high signal to the logic circuitry and output a low signal to the logic circuitry in response to power up of the second power domain. The logic circuitry is further configured to output a first value for a control signal in response to the first power domain powering up and configured to output a second value for the control signal in response to the second power domain powering up.

公开(公告)号：US09473113B1

公开(公告)日：2016-10-18

申请号：US14864101

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan ,  Lipeng Cao ,  Sai Pradeep Kochuri ,  Parissa Najdesamii

IPC: H03K3/02 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/35625

Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.

Abstract translation: 本文公开了一种用于通过具有保持特征的触发器来管理电力的集成电路（IC）。 在示例方面，IC包括恒定电源轨，可折叠电源轨，多个触发器和电源管理电路。 多个触发器的每个触发器包括耦合到可折叠电源轨的主部和耦合到恒功率轨的从部。 功率管理电路被配置为将时钟信号和保持信号组合成组合的控制信号，并将组合的控制信号提供给多个触发器的每个触发器。

公开(公告)号：US10109619B2

公开(公告)日：2018-10-23

申请号：US15174684

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Mohammed Yousuff Shariff ,  Parissa Najdesamii ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan

IPC: H01L23/538 ,  H01L27/02 ,  H01L23/535 ,  H01L27/088 ,  G06F17/50 ,  H01L21/8238

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

公开(公告)号：US20180284859A1

公开(公告)日：2018-10-04

申请号：US15471692

申请日：2017-03-28

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Rajeev Jain ,  Sassan Shahrokhinia ,  Lam Ho

IPC: G06F1/26

CPC classification number: G06F1/263 ,  H02J1/08 ,  H02J1/108

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

公开(公告)号：US11249530B1

公开(公告)日：2022-02-15

申请号：US17105253

申请日：2020-11-25

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan Pal ,  Harshat Pant ,  Abinash Roy ,  Shih-Hsin Jason Hu ,  Keith Alan Bowman

IPC: G06F1/24 ,  G06F1/30 ,  G06F1/324 ,  G05F3/24 ,  G05F1/595

Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.

公开(公告)号：US10401941B2

公开(公告)日：2019-09-03

申请号：US15425980

申请日：2017-02-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ramprasath Vilangudipitchai ,  Srijith Nair ,  Mohammad Tamjidi

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/10 ,  H03K5/13

Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.

公开(公告)号：US20180224921A1

公开(公告)日：2018-08-09

申请号：US15425980

申请日：2017-02-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ramaprasath Vilangudipitchai ,  Srijith Nair ,  Mohammad Tamjidi

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/10 ,  G06F1/3296 ,  H03K5/13 ,  Y02D10/171

Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.

公开(公告)号：US11687106B1

公开(公告)日：2023-06-27

申请号：US17662460

申请日：2022-05-09

Applicant: QUALCOMM Incorporated

Inventor： Giby Samson ,  Harshat Pant ,  Keyurkumar Karsanbhai Kansagra ,  Mohammed Yousuff Shariff ,  Vinayak Nana Mehetre

IPC: G05F1/56 ,  G06F1/26 ,  H03K17/687

CPC classification number: G05F1/56 ,  G06F1/263 ,  H03K17/687

Abstract: A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.

公开(公告)号：US11177805B1

公开(公告)日：2021-11-16

申请号：US16912521

申请日：2020-06-25

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Ravindraraj Ramaraju ,  Luis Filipe Brochado Reis ,  Tuck Boon Chan ,  Mayank Sen Sharma

IPC: H03K5/00 ,  H03K19/003

Abstract: A glitch absorbing buffer reduces glitch power in digital circuits. The glitch absorbing buffer includes a logic element configured to identify a digital logic glitch and a delay circuit configured to selectively delay one input to a logic element. The amount of delay imposed is equivalent to a pulse width of the glitch. A Schmitt trigger may amplify the low pass behavior on the input.

公开(公告)号：US11157066B2

公开(公告)日：2021-10-26

申请号：US16690680

申请日：2019-11-21

Applicant: QUALCOMM Incorporated

Inventor： Byron Murphy ,  Rajeev Jain ,  Lipeng Cao ,  Harshat Pant

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3293

Abstract: A floorplan independent and cross-current free distributed adaptive power multiplexer (APM) is disclosed. In some implementations, an APM includes a first switch path coupled between a first voltage supply rail and an output terminal, the first switch path including a first switch; a second switch path coupled between a second voltage supply rail and the output terminal, the second switch path including a second switch, wherein the first switch and the second switch are configured to select one of a first voltage supply and a second voltage supply as an output voltage supply to be output at the voltage output terminal; and a comparator coupled to the first and the second voltage supply rails, and the voltage output terminal, wherein the comparator is configured to compare the output voltage supply with one of the first and the second voltage supplies and to output a control signal.