公开(公告)号：US20230083597A1

公开(公告)日：2023-03-16

申请号：US17807125

申请日：2022-06-15

Applicant: QUALCOMM Incorporated

Inventor： Suren Mohan ,  Ren Li ,  Prajakt Kulkarni ,  Aaron Douglass Lamb

IPC: G06N3/04

Abstract: Certain aspects of the present disclosure provide a processor, comprising: a configurable nonlinear activation function circuit configured to: determine, based on a selected nonlinear activation function, a set of parameters for the nonlinear activation function; and generate output data based on application of the set of parameters for the nonlinear activation function, wherein: the configurable nonlinear activation function circuit comprises at least one nonlinear approximator comprising at least two successive linear approximators, and each linear approximator of the at least two successive linear approximators is configured to approximate a linear function using one or more function parameters of the set of parameters.

公开(公告)号：US20130156044A1

公开(公告)日：2013-06-20

申请号：US13714140

申请日：2012-12-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hans Georg Gruber ,  Magesh Hariharan ,  Julio Arceo ,  Suren Mohan ,  Aris Balatsos

IPC: H04L12/56

CPC classification number: H04L47/726 ,  G06F13/423 ,  G06F13/4291

Abstract: A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.

Abstract translation: 一种方法包括将数据从第一串行低功率芯片间媒体总线（SLIMbus）组件发送到第二SLIMbus组件。 该方法还包括经由多条SLIMbus数据线的至少第一SLIMbus数据线发送数据。

公开(公告)号：US11538509B2

公开(公告)日：2022-12-27

申请号：US17204649

申请日：2021-03-17

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Ankit Srivastava ,  Sameer Wadhwa ,  Ren Li ,  Suren Mohan

IPC: G11C11/419 ,  G11C7/12 ,  G11C7/10 ,  G11C7/18

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

公开(公告)号：US11430493B1

公开(公告)日：2022-08-30

申请号：US17204649

申请日：2021-03-17

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Ankit Srivastava ,  Sameer Wadhwa ,  Ren Li ,  Suren Mohan

IPC: G11C11/419 ,  G11C7/12 ,  G11C7/10 ,  G11C7/18

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

公开(公告)号：US09929972B2

公开(公告)日：2018-03-27

申请号：US13714140

申请日：2012-12-13

Applicant: QUALCOMM Incorporated

Inventor： Hans Georg Gruber ,  Magesh Hariharan ,  Julio Arceo ,  Suren Mohan ,  Aris J. Balatsos

IPC: G06F13/00 ,  G06F13/14 ,  H04L12/911 ,  G06F13/42

CPC classification number: H04L47/726 ,  G06F13/423 ,  G06F13/4291

Abstract: A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.