公开(公告)号：US20170257104A1

公开(公告)日：2017-09-07

申请号：US15428059

申请日：2017-02-08

Applicant: QUALCOMM Incorporated

Inventor： Hongchun Yu ,  Weiran Lin ,  Shuguang Li ,  Guangming Yin

IPC: H03L7/081 ,  H04L7/033

CPC classification number: H03L7/0814 ,  H03K2005/00058 ,  H03L7/093 ,  H04L7/0331

Abstract: Systems, methods, and apparatus are disclosed that that can improve robustness of digital phase locked loop (PLL) circuits. A method performed by a clock generation device includes generating a plurality of phase-shifted signals, each of the plurality of phase-shifted signals having a phase shift with respect to a base clock signal that is unique within the plurality of phase-shifted signals, selecting a first phase-shifted signal as an output signal, generating a first phase control word indicative of a second phase-shifted signal when the second signal has a closer phase relationship with a reference signal than the first signal, refraining from selecting the second signal as the output signal while either of the first signal and the second signal is in a first signaling state, and selecting as the output signal, the second signal when the first signal and the second signal are in a second signaling state.