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公开(公告)号：US09998099B2
公开(公告)日：2018-06-12
申请号：US14384374
申请日：2014-05-23
Applicant: QUALCOMM Incorporated
Inventor： Wenjun Su , Chulkyu Lee , Le Zhang , Guangming Yin
CPC classification number: H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
Abstract: A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
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公开(公告)号：US20170077907A1
公开(公告)日：2017-03-16
申请号：US14384374
申请日：2014-05-23
Applicant: QUALCOMM INCORPORATED
Inventor： Wenjun Su , Chulkyu Lee , Le Zhang , Guangming Yin
CPC classification number: H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
Abstract: A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
Abstract translation: 前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。 在一些方面，前馈偏置电路通过在不同的拐角条件下产生不同的偏置信号来补偿电路中的晶体管工艺角。 在一些实现中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。
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公开(公告)号：US20150194802A1
公开(公告)日：2015-07-09
申请号：US14374498
申请日：2012-02-15
Applicant: QUALCOMM INCORPORATED
Inventor： Quanqing Zhu , Guangming Yin
IPC: H02H3/22
CPC classification number: H02H3/22 , H04L25/0272 , H04L25/028
Abstract: An integrated circuit device (200) includes a first and second differential I/O pins (TRXP/TRXN) and a surge protection circuit. The surge protection circuit includes a protection transistor, a positive surge detection circuit, and a negative surge detection circuit. The protection transistor is connected between the first and second I/O pins and has a gate to receive a control signal (CTRL). The protection transistor is turned on to connect the I/O pins together if the positive surge detection circuit detects a positive surge energy on either of the I/O pins and/or if the negative surge detection circuit detects a negative surge energy on either of the I/O pins. The surge protection circuit provides increased protection for Ethernet device against undesirable energy in a manner that does not adversely affect the performance of the device.
Abstract translation: 集成电路装置（200）包括第一和第二差分I / O引脚（TRXP / TRXN）和浪涌保护电路。 浪涌保护电路包括保护晶体管，正浪涌检测电路和负浪涌检测电路。 保护晶体管连接在第一和第二I / O引脚之间，并具有接收控制信号（CTRL）的门。 如果正浪涌检测电路检测到任一个I / O引脚上的正浪涌能量和/或如果负浪涌检测电路检测到任何一个的负浪涌能量，则保护晶体管导通以将I / O引脚连接在一起 I / O引脚。 浪涌保护电路以不会对设备性能产生不利影响的方式为以太网设备提供更高的防护性能，防止不需要的能量。
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公开(公告)号：US20170257104A1
公开(公告)日：2017-09-07
申请号：US15428059
申请日：2017-02-08
Applicant: QUALCOMM Incorporated
Inventor： Hongchun Yu , Weiran Lin , Shuguang Li , Guangming Yin
CPC classification number: H03L7/0814 , H03K2005/00058 , H03L7/093 , H04L7/0331
Abstract: Systems, methods, and apparatus are disclosed that that can improve robustness of digital phase locked loop (PLL) circuits. A method performed by a clock generation device includes generating a plurality of phase-shifted signals, each of the plurality of phase-shifted signals having a phase shift with respect to a base clock signal that is unique within the plurality of phase-shifted signals, selecting a first phase-shifted signal as an output signal, generating a first phase control word indicative of a second phase-shifted signal when the second signal has a closer phase relationship with a reference signal than the first signal, refraining from selecting the second signal as the output signal while either of the first signal and the second signal is in a first signaling state, and selecting as the output signal, the second signal when the first signal and the second signal are in a second signaling state.
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