公开(公告)号：US20220157705A1

公开(公告)日：2022-05-19

申请号：US17097327

申请日：2020-11-13

Applicant: QUALCOMM Incorporated

Inventor： Wen YIN ,  Yonghao AN ,  Manuel ALDRETE

IPC: H01L23/498 ,  H01L21/48

Abstract: Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.

公开(公告)号：US20220037224A1

公开(公告)日：2022-02-03

申请号：US16941487

申请日：2020-07-28

Applicant: QUALCOMM Incorporated

Inventor： Wen YIN ,  Yonghao AN ,  Reynante Tamunan ALVARADO

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/552 ,  H01L21/56

Abstract: A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.

公开(公告)号：US20210358860A1

公开(公告)日：2021-11-18

申请号：US16874558

申请日：2020-05-14

Applicant: QUALCOMM Incorporated

Inventor： Supatta NIRAMARNKARN ,  Bin XU ,  Wen YIN ,  Yonghao AN

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/367 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a laminate substrate. The IC package also includes an active die on a surface of the laminate substrate. The IC package further includes fin-based thermal surface mount devices on the surface of the laminate substrate proximate the active die to provide an additional heat dissipation path.

公开(公告)号：US20230091182A1

公开(公告)日：2023-03-23

申请号：US17482294

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Chien-Te FENG ,  Wen YIN ,  Jay Scott SALMON

IPC: H01L23/522 ,  H01L23/36 ,  H01L23/00 ,  H01L23/60 ,  H01L21/56 ,  H01L23/31

Abstract: A device comprising a package and a board. The package includes a substrate comprising a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a back side metal layer coupled to a back side of the integrated device, a first solder interconnect coupled to the back side metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package through the plurality of solder interconnects. The first solder interconnect is coupled to the board.

公开(公告)号：US20220270995A1

公开(公告)日：2022-08-25

申请号：US17185244

申请日：2021-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wei HU ,  Dongming HE ,  Wen YIN ,  Zhe GUAN ,  Lily ZHAO

IPC: H01L23/00

Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.