公开(公告)号：US20160254793A1

公开(公告)日：2016-09-01

申请号：US15029777

申请日：2014-11-05

申请人： Wenjun SU ,  Guangming YIN ,  Quanqing ZHU ,  QUALCOMM INCORPORATED

发明人： Wenjun SU ,  Guangming YIN ,  Quanqing ZHU

IPC分类号： H03F3/45 ,  H03K5/12

CPC分类号： H03F3/45762 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45183 ,  H03F3/45609 ,  H03F3/72 ,  H03F2200/555 ,  H03F2200/72 ,  H03F2203/45288 ,  H03F2203/45301 ,  H03F2203/45511 ,  H03F2203/45638 ,  H03F2203/45644 ,  H03F2203/45702 ,  H03K5/12

摘要： Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pair of pre-driver amplifiers, a pair of n-stage circuits, and an input skew averaging circuit, wherein each of the pair of n-stage units is split into two half blocks. The input skew averaging circuit is configured to suppress the output common-mode voltage by driving the blocks with complementary digital inputs to average out a skew in a gate-to-source voltage of the pair of n-stage circuits. For certain aspects, two feed-forward capacitors may be added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.

摘要翻译： 提供了用于在驱动器中维持低输出共模电压的方法，装置和装置。 一个示例性设备包括：第一差分放大器级，被配置为提供用于该设备的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括一对预驱动器放大器，一对n级电路和输入偏差平均电路，其中， n级单元分为两个半块。 输入偏斜平均电路被配置为通过用互补数字输入驱动块来抑制输出共模电压，以平均一对n级电路的栅极至源极电压的偏移。 对于某些方面，可以添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和工作速度。

公开(公告)号：US20160013794A1

公开(公告)日：2016-01-14

申请号：US14328671

申请日：2014-07-10

申请人： QUALCOMM Incorporated

发明人： Wenjun SU ,  Le ZHANG ,  Chulkyu LEE

IPC分类号： H03K21/00

CPC分类号： H03K21/00 ,  H03K23/483

摘要： A divide-by-seven divider includes a first module clocked with a clock input, and a second module coupled to the first module and clocked with an output of the first module. The first and second modules are configured to divide the clock input by seven and to output the divided clock input. The first module may be configured to store a count between 0 and 3 in a count cycle. The divide-by-seven divider may further include a feedback module coupled between the first module and the second module that is configured to cause the first module to skip one count in the count between 0 and 3 once every other count cycle. Specifically, the first module may be configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.

摘要翻译： 一个除以七分频器包括以时钟输入为时钟的第一模块，以及耦合到第一模块并与第一模块的输出一起计时的第二模块。 第一和第二模块被配置为将时钟输入除以7并输出分频时钟输入。 第一模块可以被配置为在计数周期中存储0和3之间的计数。 除以七分频器还可以包括耦合在第一模块和第二模块之间的反馈模块，该反馈模块被配置为使得第一模块在每隔一个计数周期之间跳过0和3之间的计数中的一个计数。 具体地，第一模块可以被配置为在计数周期中逐渐地存储计数“00”，“10”，“11”和“01”，并且每隔一个计数周期跳过计数“01”，基于来自 反馈模块