公开(公告)号：US4646331A

公开(公告)日：1987-02-24

申请号：US718171

申请日：1985-04-01

申请人： Glenn L. Ely

发明人： Glenn L. Ely

IPC分类号： H03K23/44 ,  H03K23/48 ,  H03K21/00

CPC分类号： H03K23/483 ,  H03K23/44

摘要： An electronic frequency divider circuit, particularly well-adapted to implement odd-number counters, comprising a multiplicity of switched-latch stages, and in the case of an odd-number counter, further including a bypass circuit stage. Each switched-latch stage comprises a first transmission gate and two inverters configured as a latch circuit, and a second transmission gate for coupling the latch circuit to a previous stage. Even-number divider circuits may be implemented using only pairs of switched-latch stages without the bypass circuit.

摘要翻译： 一种电子分频器电路，特别适用于实现奇数计数器，其包括多个开关锁存级，并且在奇数计数器的情况下还包括旁路电路级。 每个切换锁存级包括第一传输门和配置为锁存电路的两个反相器，以及用于将锁存电路耦合到先前级的第二传输门。 偶数分频器电路可以仅使用没有旁路电路的开关锁存器对来实现。

公开(公告)号：US20180287594A1

公开(公告)日：2018-10-04

申请号：US15524375

申请日：2014-12-02

申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

发明人： Reza BAGGER

IPC分类号： H03K3/356

CPC分类号： H03K3/356104 ,  H03K3/356 ,  H03K3/356139 ,  H03K3/35625 ,  H03K3/37 ,  H03K5/15066 ,  H03K19/20 ,  H03K21/10 ,  H03K23/425 ,  H03K23/483 ,  H04B1/40

摘要： The present invention relates to an electronic latch circuit, a method, and a 4-phase generator. The electronic latch circuit comprises an output circuit comprising an output X, and an output Y. The electronic latch circuit further comprises an input circuit, comprising an input A, an input B, and a clock signal input. The input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of a first state, a second state, and a third state. The input circuit is further configured to select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state; The input circuit is further configured to select the third state upon detecting a high state on the input A, a transition on the clock signal input from a low state to a high state, and a low state on the input B, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state.

公开(公告)号：US4063114A

公开(公告)日：1977-12-13

申请号：US594402

申请日：1975-07-08

申请人： Shinji Morozumi

发明人： Shinji Morozumi

IPC分类号： G04G3/02 ,  H03K3/03 ,  H03K23/40 ,  H03K23/48 ,  H03K23/52 ,  H03K23/54 ,  H03K23/08

CPC分类号： H03K3/0307 ,  G04G3/02 ,  H03K23/40 ,  H03K23/483

摘要： A dynamic divider circuit for dividing a clock signal by n-1 where n is an odd integer is provided. The divider circuit includes n -series connected C-MOS inverter circuits, the output of the last of the series-connected inverter circuits being coupled to the input of the first of the series-connected inverter circuits to define a closed loop. n-1 inverter circuits include first switching circuits coupled thereto, the remaining inverter circuit having a second switching circuit coupled thereto, each of the switching circuits being adapted to receive the clock pulse to be divided and produce at the output of each of the C-MOS inverter circuits the divided clock signal.

摘要翻译： 提供了用于将时钟信号除以n-1的动态分频器电路，其中n是奇整数。 分频器电路包括n个连接的C-MOS反相器电路，最后串联的反相器电路的输出端连接到串联连接的反相器电路的第一个的输入端以限定闭环。 n-1个逆变器电路包括耦合到其上的第一开关电路，其余的反相器电路具有耦合到其上的第二开关电路，每个开关电路适于接收要被分频的时钟脉冲，并在每个C- MOS逆变电路分配时钟信号。

公开(公告)号：US20170324402A1

公开(公告)日：2017-11-09

申请号：US15522052

申请日：2015-12-02

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Reza Bagger

IPC分类号： H03K3/356 ,  H03K21/10

CPC分类号： H03K3/356104 ,  H03K3/356 ,  H03K3/356139 ,  H03K3/35625 ,  H03K3/37 ,  H03K5/15066 ,  H03K19/20 ,  H03K21/10 ,  H03K23/425 ,  H03K23/483 ,  H04B1/40

摘要： The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.

公开(公告)号：US20160013794A1

公开(公告)日：2016-01-14

申请号：US14328671

申请日：2014-07-10

申请人： QUALCOMM Incorporated

发明人： Wenjun SU ,  Le ZHANG ,  Chulkyu LEE

IPC分类号： H03K21/00

CPC分类号： H03K21/00 ,  H03K23/483

摘要： A divide-by-seven divider includes a first module clocked with a clock input, and a second module coupled to the first module and clocked with an output of the first module. The first and second modules are configured to divide the clock input by seven and to output the divided clock input. The first module may be configured to store a count between 0 and 3 in a count cycle. The divide-by-seven divider may further include a feedback module coupled between the first module and the second module that is configured to cause the first module to skip one count in the count between 0 and 3 once every other count cycle. Specifically, the first module may be configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.

摘要翻译： 一个除以七分频器包括以时钟输入为时钟的第一模块，以及耦合到第一模块并与第一模块的输出一起计时的第二模块。 第一和第二模块被配置为将时钟输入除以7并输出分频时钟输入。 第一模块可以被配置为在计数周期中存储0和3之间的计数。 除以七分频器还可以包括耦合在第一模块和第二模块之间的反馈模块，该反馈模块被配置为使得第一模块在每隔一个计数周期之间跳过0和3之间的计数中的一个计数。 具体地，第一模块可以被配置为在计数周期中逐渐地存储计数“00”，“10”，“11”和“01”，并且每隔一个计数周期跳过计数“01”，基于来自 反馈模块

公开(公告)号：US20090296879A1

公开(公告)日：2009-12-03

申请号：US12436766

申请日：2009-05-06

申请人： Christophe C. Beghein

发明人： Christophe C. Beghein

IPC分类号： H03K21/00

CPC分类号： H03K23/544 ,  H03K23/483 ,  H03L7/193

摘要： A counter/divider where the counter/divider comprises a: a pre-scaler operable in a first mode to divide an input signal by M and in a second mode to divide the input signal by N, where N is greater than M; a first programmable counter, and a second programmable counter; and where the first and second programmable counters are responsive to an output of the pre-scaler and an output of the first counter controls whether the pre-scaler operates in the first mode or the second mode, wherein the first counter is operable to count to greater than one.

摘要翻译： 计数器/除法器，其中计数器/除法器包括：预分频器，可在第一模式中操作以将输入信号除以M，并且在第二模式中将输入信号除以N，其中N大于M; 第一可编程计数器和第二可编程计数器; 并且其中所述第一和第二可编程计数器响应于所述预分配器的输出，并且所述第一计数器的输出控制所述预缩放器是否在所述第一模式或所述第二模式下操作，其中所述第一计数器可操作以对 大于一。

公开(公告)号：US20170244393A1

公开(公告)日：2017-08-24

申请号：US15517574

申请日：2015-05-04

申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

发明人： Reza Bagger

IPC分类号： H03K3/356 ,  H04B1/40 ,  H03K19/20

CPC分类号： H03K3/356104 ,  H03K3/356 ,  H03K3/356139 ,  H03K3/35625 ,  H03K3/37 ,  H03K5/15066 ,  H03K19/20 ,  H03K21/10 ,  H03K23/425 ,  H03K23/483 ,  H04B1/40

摘要： An electronic latch circuit (100) and a multi-phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi-phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.

公开(公告)号：US07899147B2

公开(公告)日：2011-03-01

申请号：US12436766

申请日：2009-05-06

申请人： Christophe C. Beghein

发明人： Christophe C. Beghein

IPC分类号： H03K21/00

CPC分类号： H03K23/544 ,  H03K23/483 ,  H03L7/193

摘要： A counter/divider where the counter/divider comprises a: a pre-scaler operable in a first mode to divide an input signal by M and in a second mode to divide the input signal by N, where N is greater than M; a first programmable counter, and a second programmable counter; and where the first and second programmable counters are responsive to an output of the pre-scaler and an output of the first counter controls whether the pre-scaler operates in the first mode or the second mode, wherein the first counter is operable to count to greater than one.

摘要翻译： 计数器/除法器，其中计数器/除法器包括：预分频器，可在第一模式中操作以将输入信号除以M，并且在第二模式中将输入信号除以N，其中N大于M; 第一可编程计数器和第二可编程计数器; 并且其中所述第一和第二可编程计数器响应于所述预分配器的输出，并且所述第一计数器的输出控制所述预缩放器是否在所述第一模式或所述第二模式下操作，其中所述第一计数器可操作以对 大于一。

公开(公告)号：US20100214026A1

公开(公告)日：2010-08-26

申请号：US12682352

申请日：2008-10-10

申请人： Padmanava Sen ,  Saikat Sarkar ,  Stephane Pinel ,  Joy Laskar ,  Francesco Barale

发明人： Padmanava Sen ,  Saikat Sarkar ,  Stephane Pinel ,  Joy Laskar ,  Francesco Barale

IPC分类号： H03L7/099

CPC分类号： H03K23/483 ,  H03B5/1852 ,  H03B21/02 ,  H03J3/185 ,  H03L7/099 ,  H03L7/193 ,  H03L7/24

摘要： A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

摘要翻译： 压控振荡器锁相环（VCO-PLL）系统包括实施四通道架构的压控振荡器（VCO）系统，使得两个频带支持两个通道; 锁相环（PLL）系统; 和搅拌机系统。 VCO系统还包括控制电路; 适于接收源电压的第一交叉耦合振荡器系统; 适于接收源电压的第二交叉耦合振荡器系统; 以及适于保护第一和第二交叉耦合振荡器系统的多个隔离缓冲器系统。

公开(公告)号：US20080013671A1

公开(公告)日：2008-01-17

申请号：US11718801

申请日：2005-11-09

申请人： Remco Van De Beek ,  Dominicus Leenaerts

发明人： Remco Van De Beek ,  Dominicus Leenaerts

IPC分类号： H03K23/48

CPC分类号： H03K23/483

摘要： The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CL1) frequency by an odd integer. A digital value is shifted into a set of latches based on the clock signal (CL1) and kept there a predetermined number of half clock cycles. The value is shifted into a following latch delayed with half a clock cycle of the clock signal compared with a previous latch. Then a first (Q1) and a second (Q6) intermediate signal, each provided through information stored in a latch, are interpolated for forming said first output signal (O Q). Because of this it is possible to provide an output signal having edges displaced from clock signal edges, thus allowing a higher resolution than the original clock signal has and in particular, enabling quadrature outputs from a standard odd-integer frequency divider.

摘要翻译： 本发明涉及一种用于提供具有通过将时钟信号（CL 1）频率除以奇整数而获得的频率的至少第一输出信号（O Q）的方法和装置。 数字值根据时钟信号（CL 1）移入一组锁存器，并保持预定数量的半个时钟周期。 与先前的锁存器相比，该值被移位到延迟了时钟信号的半个时钟周期的后续锁存器。 然后插入通过存储在锁存器中的信息提供的第一（Q 1）和第二（Q 6）中间信号，以形成所述第一输出信号（O Q）。 因此，可以提供具有从时钟信号边缘移位的边缘的输出信号，从而允许比原始时钟信号具有更高的分辨率，并且特别地，允许来自标准奇整数分频器的正交输出。