公开(公告)号：US20250087640A1

公开(公告)日：2025-03-13

申请号：US18465900

申请日：2023-09-12

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H10B80/00

Abstract: Disclosed are packages that may include first and second substrates with first and second chips therebetween. The first chip may be a logic chip and the second chip may be a processing near memory (PNM) chip. The active side of the first chip may face the first substrate and the active side of the second chip may face the second substrate. The first chip may be encapsulated by a first mold, and the second chip may be encapsulated by a second mold. The first and/or the second molds may be thermally conductive. A third chip (e.g., a memory) may be on the second substrate opposite the second chip. The second substrate may include very short vertical connections that connect the active sides of the second and third chips.

公开(公告)号：US20250015047A1

公开(公告)日：2025-01-09

申请号：US18348777

申请日：2023-07-07

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Jihong CHOI ,  Giridhar NALLAPATI ,  Sivakumar KUMARASAMY ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

Abstract: An integrated circuit (IC) is described. The IC includes a first die having a first semiconductor layer, a first active device layer and a first back-end-of-line (BEOL) layer. The IC also includes a second die having a second semiconductor layer, a second active device layer and a second back-end-of-line (BEOL) layer, and on the first die. The IC further includes a through substrate via (TSV) extending through the first die and the second die.

公开(公告)号：US20240422995A1

公开(公告)日：2024-12-19

申请号：US18336775

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H10B80/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.