公开(公告)号：US20250046716A1

公开(公告)日：2025-02-06

申请号：US18365791

申请日：2023-08-04

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Giridhar NALLAPATI

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A via with a modified reverse selective barrier structure and method for making the same are disclosed. In an aspect, a via structure comprises a first metal structure providing an electrical conductor (e.g., copper) oriented vertically; a second structure (e.g., cobalt) surrounding and in contact with a bottom and sides of the first metal structure; a third structure (e.g., metallic tantalum) surrounding and in contact with a bottom and sides of the second structure; a fourth structure (e.g., ruthenium) disposed beneath and in contact with a bottom of the third structure; and a fifth structure (e.g., amorphous tantalum nitride) surrounding and in contact with sides of the third structure; wherein a bottom surface of the fourth structure is in contact with a top surface of a metallization layer. In some aspects, the fifth structure is also surrounding and in contact with sides of the fourth structure.

公开(公告)号：US20150303145A1

公开(公告)日：2015-10-22

申请号：US14255820

申请日：2014-04-17

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  PR CHIDAMBARAM ,  Giridhar NALLAPATI ,  Choh Fei YEAP

IPC: H01L23/528 ,  H01L21/768 ,  G06F1/18

CPC classification number: H01L23/5283 ,  G06F1/18 ,  H01L21/76895 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates to a locally optimized integrated circuit (IC) including a first portion employing one or more metal interconnects having a first metal width and/or one or more vias having a first via width, and a second portion employing one or more metal interconnects having a second metal width and/or one or more vias having a second via width, wherein the second portion comprises a critical area of the IC, and wherein the second metal width is greater than the first metal width and the second via width is greater than the first via width. A method of locally optimizing an IC includes forming the one or more metal interconnects and/or the one or more vias in the first portion of the IC, and forming the one or more metal interconnects and/or the one or the more vias in the second portion of the integrated circuit.

Abstract translation: 本公开涉及局部优化的集成电路（IC），其包括使用具有第一金属宽度的一个或多个金属互连件的第一部分和/或具有第一通孔宽度的一个或多个通孔，以及采用一个或多个金属互连的第二部分 具有第二金属宽度和/或具有第二通孔宽度的一个或多个通孔，其中所述第二部分包括所述IC的临界区域，并且其中所述第二金属宽度大于所述第一金属宽度，并且所述第二通孔宽度更大 比第一个通道宽度。 局部优化IC的方法包括在IC的第一部分中形成一个或多个金属互连和/或一个或多个通孔，以及形成一个或多个金属互连和/或一个或多个通孔 集成电路的第二部分。

公开(公告)号：US20150064864A1

公开(公告)日：2015-03-05

申请号：US14538617

申请日：2014-11-11

Applicant: QUALCOMM Incorporated

Inventor： Benjamin John BOWERS ,  James W. HAYWARD ,  Charanya GOPAL ,  Gregory Christopher BURDA ,  Robert J. BUCKI ,  Chock H. GAN ,  Giridhar NALLAPATI ,  Matthew D. YOUNGBLOOD ,  William R. FLEDERBACH

IPC: G06F17/50 ,  H01L27/115 ,  H01L29/66 ,  H01L21/22

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/22 ,  H01L27/092 ,  H01L27/11521 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/66825 ,  Y02P90/265

Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Abstract translation: 用于设计集成电路的单元库，该库包括连续扩散兼容（CDC）单元。 CDC单元包括电连接到电源轨的p掺杂扩散区，并且连接于CDC单元的左边缘到右边缘; 第一多晶硅栅极，设置在p掺杂扩散区上方并电连接到p掺杂扩散区; 电连接到接地导轨并从左边缘到右边缘连续的n掺杂扩散区域; 第二多晶硅栅极，其设置在所述n掺杂扩散区域上方并电连接到所述n掺杂扩散区域; 设置在p掺杂和n掺杂扩散区上并靠近左边缘的左浮动多晶硅栅极; 以及设置在p掺杂和n掺杂扩散区域上并且靠近右边缘的右浮动多晶硅栅极。

公开(公告)号：US20230072667A1

公开(公告)日：2023-03-09

申请号：US17470274

申请日：2021-09-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Lixin GE ,  Giridhar NALLAPATI

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Disclosed are examples of a device and method of fabricating a device including a first top contact, a second top contact, adjacent the first top contact, a first mesa disposed below the first top contact and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and electrically coupled to the first top contact.

公开(公告)号：US20220336351A1

公开(公告)日：2022-10-20

申请号：US17234377

申请日：2021-04-19

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L21/768

Abstract: In an aspect, a system on a chip (SOC) includes a plurality of function blocks, including a first function block and a second function block, co-located on the SOC. The SOC includes a first metal layer, a first dielectric layer located on top of the first metal layer, and a first via located in the first dielectric layer and used in the first function block. The SOC includes a second via located in the first dielectric layer and used in the second function block and a second metal layer located on the first dielectric layer. The second metal layer comprises a first set of connections used in the first function block and a second set of connections used in the second function block. The first set of connections is different from the second set of connections. The SOC includes a second dielectric layer located on the first dielectric layer.

公开(公告)号：US20210143056A1

公开(公告)日：2021-05-13

申请号：US16676715

申请日：2019-11-07

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Certain aspects of the present disclosure generally relate to methods of fabricating integrated circuits. An example method generally includes forming a first cavity in a first layer disposed above a second layer and filling at least a portion of the first cavity with a dielectric material disposed above the second layer. The method further includes forming a second cavity in the dielectric material such that the dielectric material remaining in the first cavity is disposed on (e.g., conforms to) lateral surfaces of the first layer in the first cavity and forming a dielectric spacer comprising a segment of the remaining dielectric material in the first cavity. The method also includes forming a first conductor, in the first layer or the second layer, that is laterally spaced from a second conductor based at least in part on a width of the dielectric spacer.

公开(公告)号：US20220336607A1

公开(公告)日：2022-10-20

申请号：US17235491

申请日：2021-04-20

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Giridhar NALLAPATI

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/417 ,  H01L27/088

Abstract: Disclosed are apparatuses including a transistor cell and methods of fabricating the transistor cell. The transistor cell may include a substrate, an active region and a gate having a gate contact in the active region. The transistor cell may further include a first portion of a spacer of the gate contact formed from a first material, and a second portion of the spacer of the gate contact formed from a second material.

公开(公告)号：US20210167006A1

公开(公告)日：2021-06-03

申请号：US16702335

申请日：2019-12-03

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  John Jianhong ZHU ,  Giridhar NALLAPATI

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Disclosed are standard cells and methods for fabricating standard cells used in semiconductor device design and fabrication. Aspects disclosed include a standard cell having a plurality of wide metal lines. The wide metal lines being formed from copper. The standard cell also includes a plurality of narrow metal lines. The narrow metal lines are formed from a material that has a lower resistance than copper for line widths on the order of twelve nanometers or less.

公开(公告)号：US20210125862A1

公开(公告)日：2021-04-29

申请号：US16664677

申请日：2019-10-25

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Jun CHEN ,  Giridhar NALLAPATI

IPC: H01L21/768

Abstract: Aspects of the disclosure are directed to super via integration. In accordance with one aspect, an apparatus with super via integration in an integrated circuit including a first metal layer; a second metal layer, wherein the second metal layer is adjacent to the first metal layer; a third metal layer, wherein the third metal layer is adjacent to the second metal layer and is non-adjacent to the first metal layer; and a super via interconnecting the first metal layer and the third metal layer through a dielectric material, wherein the super via is filled with a selective metal.

公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC: H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.