公开(公告)号：US09852859B2

公开(公告)日：2017-12-26

申请号：US14981183

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Dorav Kumar ,  Bilal Zafar ,  Ramaprasath Vilangudipitchai ,  Venkatasubramanian Narayanan ,  Xi Luo

IPC: H01H47/00 ,  H03K19/00

CPC classification number: H01H47/00 ,  H03K19/0008

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.

公开(公告)号：US20170186576A1

公开(公告)日：2017-06-29

申请号：US14981183

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Dorav Kumar ,  Bilal Zafar ,  Ramaprasath Vilangudipitchai ,  Venkatasubramanian Narayanan ,  Xi Luo

IPC: H01H47/00

CPC classification number: H01H47/00 ,  H03K19/0008

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.