公开(公告)号：US10163474B2

公开(公告)日：2018-12-25

申请号：US15273606

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Masoud Zamani ,  Bilal Zafar ,  Venkatasubramanian Narayanan

IPC: G11C7/22 ,  H03K5/133 ,  H03K19/20 ,  H03K5/00

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

公开(公告)号：US20150194209A1

公开(公告)日：2015-07-09

申请号：US14165702

申请日：2014-01-28

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Venkatasubramanian Narayanan ,  Kendrick Hoy Leong Yuen

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C7/065 ,  G11C7/08 ,  G11C7/222 ,  G11C11/1673 ,  G11C2013/0042 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems are disclosed. In one embodiment, sense amplifier is provided. The sense amplifier comprises a differential sense input coupled to bit line. The sense amplifier also comprises a differential reference input coupled to reference line. First inverter inverts first inverter input into first inverter output coupled to second inverter input of second inverter, first inverter output configured to provide state of bitcell. Second inverter inverts second inverter input into second inverter output coupled to first inverter input. Control circuit couples differential reference input to first inverter and differential sense input to second inverter in latch mode, and decouples differential reference input to first inverter and differential sense input to second inverter in sensing mode to provide sensed state of bitcell on first inverter output.

Abstract translation: 公开了采用控制电路的感应放大器，用于在状态检测期间去耦电阻性存储器感测输入以防止电流反向注入，以及相关方法和系统。 在一个实施例中，提供了读出放大器。 感测放大器包括耦合到位线的差分感测输入。 读出放大器还包括耦合到参考线的差分参考输入。 第一变频器将第一变频器输入转换为与第二变频器的第二变频器输入相连接的第一变频器输出，第一变频器输出被配置为提供位单元的状态。 第二个变频器将第二个变频器输入转换成与第一个变频器输入相连的第二个变频器输出。 控制电路在锁存模式下将差分参考输入与第一个反相器和差分检测输入耦合到第二个反相器，在感测模式下将差分参考输入与第一个反相器和差分检测输入去耦到第二个反相器，以提供第一个反相器输出上的位单元的检测状态。

公开(公告)号：US20180074126A1

公开(公告)日：2018-03-15

申请号：US15263059

申请日：2016-09-12

Applicant: QUALCOMM Incorporated

Inventor： Bilal Zafar ,  Rakesh Vattikonda ,  De Lu ,  Venkatasubramanian Narayanan ,  Masoud Zamani ,  Joseph Fang

IPC: G01R31/317 ,  G11C7/22 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318552 ,  G11C7/22

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.

公开(公告)号：US09564210B2

公开(公告)日：2017-02-07

申请号：US14720930

申请日：2015-05-25

Applicant: QUALCOMM Incorporated

Inventor： Venkatasubramanian Narayanan ,  Alex Dongkyu Park

IPC: G11C11/00 ,  G11C11/417 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/419 ,  G11C29/04 ,  G11C29/12005 ,  G11C29/50004 ,  G11C2029/0401 ,  G11C2029/1204 ,  H01L27/1116

Abstract: A static random access memory (SRAM) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor. An aging sensor is coupled between the first bitcell and the second bitcell to determine an amount of aging associated with the aging transistor. In one aspect, the amount of aging associated with the aging transistor is determined based on a difference between a voltage or current associated with the aging transistor and a voltage or current associated with the non-aging transistor.

Abstract translation: 静态随机存取存储器（SRAM）包括第一位单元和第二位单元。 第一位单元包括老化晶体管，第二位单元包括非时效晶体管。 老化传感器耦合在第一位单元和第二位单元之间以确定与老化晶体管相关联的老化量。 在一个方面，与老化晶体管相关联的老化量基于与老化晶体管相关的电压或电流与与非老化晶体管相关联的电压或电流之间的差来确定。

公开(公告)号：US20150279452A1

公开(公告)日：2015-10-01

申请号：US14228091

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung YOON ,  Derek Xiaoxiang Yang ,  Alex Dongkyu Park ,  Venkatasubramanian Narayanan

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1057 ,  G11C2207/005

Abstract: A memory and a method for operating the memory having a precharge circuit with inputs of multiple voltage domains are provided. In one aspect, a memory includes a bitline and one or more storage elements coupled to the bitline. The one or more storage elements are configured to operate in a first voltage domain using a first supply voltage. A pull-up circuit is configured to pull up the bitline to a second supply voltage in a second voltage domain. The pull-up circuit is responsive to a first control signal in the first voltage domain and a second control signal in the second voltage domain. The first supply voltage is different than the second supply voltage.

Abstract translation: 提供一种用于操作具有具有多个电压域的输入的预充电电路的存储器的存储器和方法。 在一个方面，存储器包括位线和耦合到位线的一个或多个存储元件。 一个或多个存储元件被配置为使用第一电源电压在第一电压域中操作。 上拉电路被配置为在第二电压域中将位线上拉到第二电源电压。 上拉电路响应于第一电压域中的第一控制信号和第二电压域中的第二控制信号。 第一电源电压不同于第二电源电压。

公开(公告)号：US20150100842A1

公开(公告)日：2015-04-09

申请号：US14046084

申请日：2013-10-04

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli ,  Sagar Suresh Sabade ,  Bilal Zafar

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract translation: 提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。 主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有 用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。

公开(公告)号：US09859891B1

公开(公告)日：2018-01-02

申请号：US15192872

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Dorav Kumar ,  Venkatasubramanian Narayanan ,  Bala Krishna Thalla ,  Seid Hadi Rasouli ,  Radhika Vinayak Guttal ,  Sivakumar Paturi

IPC: H03K19/003 ,  H01L27/02 ,  H01L23/528 ,  H01L27/088 ,  H03K19/177

CPC classification number: H03K19/00361 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H03K19/17736 ,  H03K19/17744

Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.

公开(公告)号：US09165641B2

公开(公告)日：2015-10-20

申请号：US14106575

申请日：2013-12-13

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Ashish Akhilesh ,  Venkatasubramanian Narayanan

IPC: G11C11/00 ,  G11C11/417 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C7/12

Abstract: A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an N-type semiconductor device and a P-type semiconductor device. The memory device biasing circuit further includes a bias adjustment circuit coupled to the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage.

Abstract translation: 公开了一种存储器件偏置电路，该电路具有一对半导体器件，其被耦合以接收电源电压，该电源电压具有适于在有源模式下操作存储器件的电源电压电平，并可操作以向存储器件提供可调节的偏置电压， 大于在数据保持模式下操作存储器件的最小电压电平。 所述一对半导体器件包括第一半导体器件; 以及包括与第一半导体器件相反的半导体器件的第二半导体器件，使得该对半导体器件包括N型半导体器件和P型半导体器件中的每一个。 存储器件偏置电路还包括耦合到第二半导体器件并被配置为基于电源电压来调整第二半导体器件的操作的偏置调整电路。

公开(公告)号：US09087579B1

公开(公告)日：2015-07-21

申请号：US14165702

申请日：2014-01-28

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Venkatasubramanian Narayanan ,  Kendrick Hoy Leong Yuen

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C7/065 ,  G11C7/08 ,  G11C7/222 ,  G11C11/1673 ,  G11C2013/0042 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems are disclosed. In one embodiment, sense amplifier is provided. The sense amplifier comprises a differential sense input coupled to bit line. The sense amplifier also comprises a differential reference input coupled to reference line. First inverter inverts first inverter input into first inverter output coupled to second inverter input of second inverter, first inverter output configured to provide state of bitcell. Second inverter inverts second inverter input into second inverter output coupled to first inverter input. Control circuit couples differential reference input to first inverter and differential sense input to second inverter in latch mode, and decouples differential reference input to first inverter and differential sense input to second inverter in sensing mode to provide sensed state of bitcell on first inverter output.

Abstract translation: 公开了采用控制电路的感应放大器，用于在状态检测期间去耦电阻性存储器感测输入以防止电流反向注入，以及相关方法和系统。 在一个实施例中，提供了读出放大器。 感测放大器包括耦合到位线的差分感测输入。 读出放大器还包括耦合到参考线的差分参考输入。 第一变频器将第一变频器输入转换为与第二变频器的第二变频器输入相连接的第一变频器输出，第一变频器输出被配置为提供位单元的状态。 第二个变频器将第二个变频器输入转换成与第一个变频器输入相连的第二个变频器输出。 控制电路在锁存模式下将差分参考输入与第一个反相器和差分检测输入耦合到第二个反相器，在感测模式下将差分参考输入与第一个反相器和差分检测输入去耦到第二个反相器，以提供第一个反相器输出上的位单元的检测状态。

公开(公告)号：US09081060B2

公开(公告)日：2015-07-14

申请号：US14046084

申请日：2013-10-04

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli ,  Sagar Suresh Sabade ,  Bilal Zafar

IPC: G01R31/3177 ,  G01R31/3185 ,  G06F11/27 ,  G01R31/3187

CPC classification number: G01R31/3177 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract translation: 提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。 主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有 用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。