公开(公告)号：US10128846B2

公开(公告)日：2018-11-13

申请号：US15478063

申请日：2017-04-03

Applicant: QUALCOMM Incorporated

Inventor： Yeshwanth Kumar Mallavajula ,  Wilson Chen ,  Chiew-Guan Tan

IPC: H03K19/00 ,  H03K17/687 ,  H03K19/0185 ,  H03K17/06

Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.

公开(公告)号：US20180287609A1

公开(公告)日：2018-10-04

申请号：US15478063

申请日：2017-04-03

Applicant: QUALCOMM Incorporated

Inventor： Yeshwanth Kumar Mallavajula ,  Wilson Chen ,  Chiew-Guan Tan

IPC: H03K19/00 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K19/0013 ,  H03K3/356017 ,  H03K3/356034 ,  H03K3/35613 ,  H03K17/063 ,  H03K17/6872 ,  H03K19/018521 ,  H03K19/018528

Abstract: The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.