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1.发明公开公开(公告)号：US20240348837A1
公开(公告)日：2024-10-17
申请号：US18631748
申请日：2024-04-10
IPC分类号： H04N19/82 , H04N19/117 , H04N19/172 , H04N19/176
CPC分类号： H04N19/82 , H04N19/117 , H04N19/172 , H04N19/176
摘要： A device for decoding video data receives a picture of video data; reconstructs a block of the picture of video data to generate a reconstructed block; and performs a neural network (NN)-based filter process on the reconstructed block to generate a filtered block, wherein the NN-based filter process includes performing a plurality of separable convolutions in parallel with a point-wise input convolution.
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公开(公告)号：US20240283925A1
公开(公告)日：2024-08-22
申请号：US18442955
申请日：2024-02-15
IPC分类号： H04N19/117 , H04N19/105 , H04N19/176
CPC分类号： H04N19/117 , H04N19/105 , H04N19/176
摘要： A video coder is configured to perform a neural network (NN)-based filter process on reconstructed blocks of vide data. In one example, a video coder may receive a picture of video data, and reconstruct a block of the picture of video data to generate a reconstructed block. The video coder may perform the NN-based filter process on the reconstructed block to generate a filtered block, wherein the NN-based filter process includes performing a plurality separable convolutions to approximate a multi-dimensional convolution.
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3.发明申请公开(公告)号：US20180174623A1
公开(公告)日：2018-06-21
申请号：US15381587
申请日：2016-12-16
发明人： Fei Xu , Rakesh Vattikonda , Dina McKinney , Zhen Chen , Yun Li , Zhenbiao Ma , De Lu
CPC分类号： G11C7/1012 , G11C7/222
摘要： An apparatus and method are disclosed for transferring data from a first core to a second core of an integrated circuit (IC). The first core includes first and second memory blocks (e.g., first and second portions of a first-in-first-out (FIFO) memory coupled to first and second pre-multiplexers, respectively). The second core includes a multiplexer including first and second inputs coupled to the first and second memory blocks, respectively. Additionally, the second core includes a read controller configured to generate a first read control signal to cause the first and second memory blocks to transfer data to the first and second inputs of the multiplexer, respectively; and generate a second read control signal to cause the multiplexer to transfer data from the first and inputs to an output of the multiplexer.
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公开(公告)号：US20240282012A1
公开(公告)日：2024-08-22
申请号：US18442622
申请日：2024-02-15
IPC分类号： G06T9/00 , H04N19/105 , H04N19/176 , H04N19/192 , H04N19/70 , H04N19/82
CPC分类号： G06T9/002 , H04N19/105 , H04N19/176 , H04N19/192 , H04N19/70 , H04N19/82
摘要： A video encoder and video decoder are configured to perform a neural network (NN)-based filter process on reconstructed blocks of video data. In one example, the NN-based filter process uses reconstruction samples of the block, prediction samples of the block, and supplementary data related to the block as inputs. The NN-based filter process includes an initial processing of one or more types of the supplementary data with fewer computations relative to the initial processing of the reconstruction samples and the prediction samples.
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公开(公告)号：US20180189179A1
公开(公告)日：2018-07-05
申请号：US15423889
申请日：2017-02-03
IPC分类号： G06F12/0811 , G06F12/0875 , G06F12/0846
CPC分类号： G06F12/0811 , G06F12/0846 , G06F12/0853 , G06F12/0875 , G06F2212/1016 , G06F2212/455
摘要： A cache memory may receive, from a client, a request for a long cache line of data. The cache memory may receive, from a memory, the requested long cache line of data. The cache memory may store the requested long cache line of data into a plurality of data stores across a plurality of memory banks as a plurality of short cache lines of data distributed across the plurality of data stores in the cache memory. The cache memory may also store a plurality of tags associated with the plurality of short cache lines of data into one of a plurality of tag stores in the plurality of memory banks.
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