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公开(公告)号：US20180189179A1
公开(公告)日：2018-07-05
申请号：US15423889
申请日：2017-02-03
Applicant: QUALCOMM Incorporated
IPC: G06F12/0811 , G06F12/0875 , G06F12/0846
CPC classification number: G06F12/0811 , G06F12/0846 , G06F12/0853 , G06F12/0875 , G06F2212/1016 , G06F2212/455
Abstract: A cache memory may receive, from a client, a request for a long cache line of data. The cache memory may receive, from a memory, the requested long cache line of data. The cache memory may store the requested long cache line of data into a plurality of data stores across a plurality of memory banks as a plurality of short cache lines of data distributed across the plurality of data stores in the cache memory. The cache memory may also store a plurality of tags associated with the plurality of short cache lines of data into one of a plurality of tag stores in the plurality of memory banks.
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2.发明申请公开(公告)号：US20180174623A1
公开(公告)日：2018-06-21
申请号：US15381587
申请日：2016-12-16
Applicant: QUALCOMM Incorporated
Inventor： Fei Xu , Rakesh Vattikonda , Dina McKinney , Zhen Chen , Yun Li , Zhenbiao Ma , De Lu
CPC classification number: G11C7/1012 , G11C7/222
Abstract: An apparatus and method are disclosed for transferring data from a first core to a second core of an integrated circuit (IC). The first core includes first and second memory blocks (e.g., first and second portions of a first-in-first-out (FIFO) memory coupled to first and second pre-multiplexers, respectively). The second core includes a multiplexer including first and second inputs coupled to the first and second memory blocks, respectively. Additionally, the second core includes a read controller configured to generate a first read control signal to cause the first and second memory blocks to transfer data to the first and second inputs of the multiplexer, respectively; and generate a second read control signal to cause the multiplexer to transfer data from the first and inputs to an output of the multiplexer.
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