公开(公告)号：US20040230979A1

公开(公告)日：2004-11-18

申请号：US10714696

申请日：2003-11-17

Applicant: Quadrics Limited

Inventor： Jon Beecroft ,  David Hewson ,  Moray McLaren

IPC: G06F009/46

CPC classification number: G06F13/387

Abstract: A computer network (1) comprises:nullat least two processing nodes each having a processor (4) on which one or more user processes are executed and a respective network interface (2); and a switching network (3) which operatively connects the at least two processing nodes together, each network interface (2) including a command processor and a memory wherein the command processor of said network interface (2) is configured to allocate exclusively to a user process being executed on the processor (4) with which the network interface (2) is associated one or more segments of addressable memory in said network interface memory as a respective one or more command queues The network interface (2) is capable of processing command data at high rates and with low latencies whilst maintaining the security of individual user processes.

Abstract translation: 计算机网络（1）包括： - 至少两个处理节点，每个处理节点具有执行一个或多个用户进程的处理器（4）和相应的网络接口（2）; 以及将所述至少两个处理节点可操作地连接在一起的交换网络（3），每个网络接口（2）包括命令处理器和存储器，其中所述网络接口（2）的命令处理器被配置为专门地分配给用户 所述处理器在所述网络接口（2）与所述网络接口存储器中的可寻址存储器的一个或多个段相关联的处理器（4）上执行，作为相应的一个或多个命令队列。所述网络接口（2）能够处理命令 数据在高速率和低延迟同时保持个人用户进程的安全性。

公开(公告)号：US20040221128A1

公开(公告)日：2004-11-04

申请号：US10712218

申请日：2003-11-13

Applicant: Quadrics Limited

Inventor： Jon Beecroft ,  David Hewson ,  Moray McLaren

IPC: G06F012/08

CPC classification number: G06F12/1018 ,  G06F12/1027 ,  G06F12/1072 ,  G06F2212/652

Abstract: A computer network (1) comprises:- a plurality of processing nodes, at least two of which each having respective addressable memories and respective network interfaces (2); and a switching network (3) which operatively connects the plurality of processing nodes together, each network interface (2) including a memory management unit (8a) having associated with it a memory in which is stored (a) at least one mapping table for mapping 64 bit virtual addresses to the physical addresses of the addressable memory of the respective processing node; and (b) instructions for applying a compression algorithm to said virtual addresses, the at least one mapping table comprising a plurality of virtual addresses and their associated physical addresses ordered with respect to compressed versions of the 64 bit virtual addresses. The network interface (2) provides visibility across the network of areas of the memory of individual processing nodes in a way which supports full scalability of the network.

Abstract translation: 计算机网络（1）包括： - 多个处理节点，其中至少两个具有各自的可寻址存储器和相应的网络接口（2）; 以及将所述多个处理节点可操作地连接在一起的交换网络（3），每个网络接口（2）包括与其相关联的存储器的存储器管理单元（8a），其中存储有（a）至少一个映射表， 将64位虚拟地址映射到相应处理节点的可寻址存储器的物理地址; 以及（b）用于将压缩算法应用于所述虚拟地址的指令，所述至少一个映射表包括关于64位虚拟地址的压缩版本排序的多个虚拟地址及其相关联的物理地址。 网络接口（2）以支持网络的完全可扩展性的方式提供各个处理节点的存储器区域的网络的可见性。