公开(公告)号：US20170214539A1

公开(公告)日：2017-07-27

申请号：US15007804

申请日：2016-01-27

Applicant: Quanta Computer Inc.

Inventor： Wei-Yi CHU ,  Chia-Feng CHENG ,  Chia-Ming LIANG ,  Meng-Huan LU

IPC: H04L12/18 ,  H04L12/26

Abstract: A server system may include a plurality of internal hubs communicatively coupled to a plurality of server nodes. The plurality of internal hubs may communicate with an external hub to transmit broadcast traffic to reach a designated server node. A hub controller, a routing device coupled to the plurality of internal hubs, may select an internal hub from among a plurality of internal hubs based on a link status and a set of hub selection rules. Based on a status of active link and a relative priority of internal hubs, an internal hub is selected as a transmission channel to receive broadcast traffic from the external hub and direct the broadcast traffic to a corresponding server node.

公开(公告)号：US20170212858A1

公开(公告)日：2017-07-27

申请号：US15007753

申请日：2016-01-27

Applicant: Quanta Computer Inc.

Inventor： Wei-Yi CHU ,  Chia-Feng CHENG ,  Kai CHANG ,  Chih-Yu CHEN

IPC: G06F13/40 ,  G06F13/28 ,  G06F12/02 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F12/0246 ,  G06F13/287 ,  G06F13/4282 ,  G06F2212/7208

Abstract: A system for switching between a high performance mode and dual path mode is disclosed. The system includes a first device, a second device, a third device, and a switch configured to receive control signals, and in response causing the switch to selectively couple one or more first lanes of the first device or one or more second lanes of the second device to third lanes of the third device to yield enabled lanes. The system also include a number of the enabled lanes is less than or equal to a number of the third lanes, and the switch is configured to route the enabled lanes associated with the first device to a first portion of the third lanes in an increasing order and to route the enabled lanes associated with the second device to a second portion of the third lanes in a decreasing order.

公开(公告)号：US20180004695A1

公开(公告)日：2018-01-04

申请号：US15199504

申请日：2016-06-30

Applicant: Quanta Computer Inc.

Inventor： Wei-Yi CHU ,  Chia-Feng CHENG ,  Kai CHANG ,  Chih-Yu CHEN

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F3/0688 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4095

Abstract: An apparatus having a first interface of a first type supporting a plurality of data ports, a second interface of a second type supporting at least a portion of the plurality data ports, and a third interface of the second type. The apparatus also including a switching module coupled to a control port of the first interface and configured for selectably coupling the plurality of data ports to at least one of the second interface and the third interface based on a signal at the control port.