公开(公告)号：US10224100B2

公开(公告)日：2019-03-05

申请号：US15100167

申请日：2014-12-03

Applicant: RAMBUS INC.

Inventor： Deepak Chandra Sekar ,  Brent S. Haukness ,  Bruce L. Bateman

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.

公开(公告)号：US10658037B2

公开(公告)日：2020-05-19

申请号：US16209479

申请日：2018-12-04

Applicant: RAMBUS INC.

Inventor： Deepak Chandra Sekar ,  Brent S. Haukness ,  Bruce L. Bateman

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.