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    Memory component with error-detect-correct code interface
    1.
    发明授权
    Memory component with error-detect-correct code interface 有权

    公开(公告)号：US11762737B2

    公开(公告)日：2023-09-19

    申请号：US17956516

    申请日：2022-09-29

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: H03M13/27 ,  H04L27/34 ,  H04L1/00 ,  H03M13/25 ,  G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/1048

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    MEMORY MODULE WITH DEDICATED REPAIR DEVICES
    2.
    发明申请
    MEMORY MODULE WITH DEDICATED REPAIR DEVICES 有权

    公开(公告)号：US20220004472A9

    公开(公告)日：2022-01-06

    申请号：US16670798

    申请日：2019-10-31

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

    IPC: G06F11/20 ,  G11C29/52 ,  G11C11/4093

    Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

    Memory component with error-detect-correct code interface
    4.
    发明授权
    Memory component with error-detect-correct code interface 有权

    公开(公告)号：US10452478B2

    公开(公告)日：2019-10-22

    申请号：US15794164

    申请日：2017-10-26

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: G11C29/00 ,  G06F11/10

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    Fractional program commands for memory devices
    6.
    发明授权
    Fractional program commands for memory devices 有权

    公开(公告)号：US11651823B2

    公开(公告)日：2023-05-16

    申请号：US16953182

    申请日：2020-11-19

    Applicant: Rambus Inc.

    Inventor： Brent S. Haukness ,  Ian Shaeffer ,  Gary Bela Bronner

    IPC: G11C16/10 ,  G06F3/06

    CPC classification number: G11C16/10 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0688 ,  G06F2212/7204

    Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

    Memory component with error-detect-correct code interface
    7.
    发明授权
    Memory component with error-detect-correct code interface 有权

    公开(公告)号：US10884860B2

    公开(公告)日：2021-01-05

    申请号：US16565848

    申请日：2019-09-10

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: G11C29/00 ,  G06F11/10

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    DYNAMIC MEMORY RANK CONFIGURATION
    9.
    发明申请
    DYNAMIC MEMORY RANK CONFIGURATION 审中-公开
    动态记忆排名配置

    公开(公告)号：US20160071608A1

    公开(公告)日：2016-03-10

    申请号：US14940084

    申请日：2015-11-12

    Applicant: Rambus Inc.

    Inventor： Gary B. Bronner ,  Brent S. Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/06 ,  H01L21/324

    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

    Abstract translation: 存储器控制组件内的控制逻辑在相应的时间向存储器模块输出第一和第二存储器读取命令，存储器模块具有置于其上的存储器组件。 存储器控制组件内的接口电路响应于第一存储器读取命令分别经由第一多个数据路径从第一多个存储器组件同时接收第一读取数据，并且从第二个多个 所述存储器组件分别响应于所述第二存储器读取命令经由第二多个数据路径，所述第一多个存储器组件包括不包括在所述第二多个存储器组件中的至少一个存储器组件，反之亦然。

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