公开(公告)号：US12009056B2

公开(公告)日：2024-06-11

申请号：US17861424

申请日：2022-07-11

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Fu-Chin Tsai ,  Ger-Chih Chou ,  Chun-Chi Yu ,  Chih-Wei Chang ,  Shih-Han Lin

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/222 ,  G11C7/1012 ,  G11C7/109

摘要： The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least ┌P┐.

公开(公告)号：US10998020B1

公开(公告)日：2021-05-04

申请号：US16866886

申请日：2020-05-05

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Fu-Chin Tsai ,  Chun-Chi Yu ,  Chih-Wei Chang ,  Gerchih Chou ,  Kuo-Wei Chi ,  Shih-Chang Chen ,  Shih-Han Lin ,  Min-Han Tsai

IPC分类号： G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  H03K7/08 ,  G11C8/18

摘要： The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.

公开(公告)号：US10522204B1

公开(公告)日：2019-12-31

申请号：US16183348

申请日：2018-11-07

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Chun-Chi Yu ,  Fu-Chin Tsai ,  Shih-Han Lin ,  Chih-Wei Chang ,  Gerchih Chou

IPC分类号： G11C7/22 ,  G06F3/06

摘要： A memory signal phase difference calibration circuit includes: a clock generator providing clocks allowing a physical layer (PHY) circuit of DDR SDRAM to generate a data input/output signal (DQ) and a data strobe signal (DQS) for accessing a storage circuit; a calibration control circuit outputting a phase control signal according to an adjustment range to adjust the phase of a target signal (DQ or DQS), and outputting a calibration control signal; an access control circuit reading storage data representing predetermined data from the storage circuit according to the calibration control signal; a comparison circuit comparing the predetermined data with the storage data to output a result allowing the calibration control circuit to alter the adjustment range accordingly; and a phase controller outputting a clock control signal according to the phase control signal to set the phase of a target clock used for the PHY circuit generating the target signal.